Boots – shoes – and leggings
Patent
1983-06-27
1986-12-23
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 1300
Patent
active
046316671
ABSTRACT:
An asynchronous bus multiprocessor system where a plurality of microprogrammed processors communicate with a working memory through a common bus. Microinstructions are read out from working memory. At least one of the processors, in addition to conventional bus interface registers for latching of data, address and commands to be forwarded to the working memory through the bus, is provided with an additional interface register, devoted to the latching of a microinstruction address for a microinstruction to be read out from the working memory. The system is further provided with a multiplexer for selectively loading a microinstruction register either from a microprogram control memory or from the system common bus, via a direct path established between the system common bus and an input set of the multiplexer. The microinstruction transfer speed from working memory to the processor is further enhanced by means of different timing for the data transfer through the bus and the microinstruction transfer through the bus. In the case of data transfer a bus access cycle is started at the end of the processor cycle during which the relevant bus interface register is loaded. In the case of microinstruction read out from working memory, the additional interface register is loaded at the beginning of a processor cycle concurrently with the request of bus access cycle, so that the two overlap.
REFERENCES:
patent: 3949372 (1976-04-01), Brioschi
patent: 4302808 (1981-11-01), Zanchi
Zanchi Vittorio
Zulian Ferruccio
Chan Emily Yue
Honeywell Information Systems Italia
Prasinos Nicholas
Solakian John S.
Zache Raulfe B.
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