Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-08-14
2002-08-06
Nguyen, Chau (Department: 2663)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
Reexamination Certificate
active
06430186
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to electronic circuits and to digital communication. More particularly, the present invention relates to a bit-table calendar for translating digital communications between a time-division multiplexed (TDM) domain and a cell-based asynchronous transfer mode (ATM) domain.
The present invention has a number of applications in advanced telecommunication systems and networks. One envisioned application of the invention is for use in state-of-the-art telephone central office (CO) switching systems to connect local T1 TDM lines in one area to T1 TDM lines in different area through a high performance ATM backbone. Another application would be at the site of an institutional customer such as a company or research or educational institution for connecting a T1 line provided by a public telephone network to a local ATM network.
This discussion presupposes some familiarity with ATM cell-based switch methodology, such as that described in detail in co-assigned U.S. patent application Ser. No. 08/235,006, filed Apr. 28, 1994, now U.S. Pat. No. 5,583,861, entitled ATM ARCHITECTURE AND SWITCHING ELEMENT, which is hereby incorporated by reference. The present discussion also presumes some familiarity with commonly TDM technology such as that employed in widely available T1 lines used and leased by public telephone companies throughout the United States and E1 lines used in other countries.
Explanation of both the prior art and the invention will be better understood with reference to specific examples, however this should not be taken to limit the invention to the particular examples described. The invention is generalizable to other similar types of communication interfaces and the invention should therefore not be limited except as provided in the attached claims.
T1 type TDM service is a widely used, medium speed digital communication service provided by, among others, public telephone companies in the United States. E1 service is a similar service provided in Europe. A T1/E1 line is conceived of as a single point to point serial digital communication line operating at an overall data speed of 1.544 Mb/s for T1 and 2.098 Mb/s for E1. Serial data on a T1 or E1 line is divided into 125 microsecond intervals, called frames, and each frame is further divided into TDM time slots. T1 lines have 24 slots per frame, and E1 lines have 32 slots per frame. Each T1/E1 slot has a speed of 64 Kb/s: {fraction (1/24)}th of the overall T1 speed or {fraction (1/32)}nd of the overall E1 speed. Each T1/E1 slot can carry an independent serial digital data signal, for example a digitally encoded telephone call. Therefore a single T1 line can carry 24 concurrent telephone calls. Data is routed to a particular telephone call used on which slot it is located. The format of data on a T1 line is shown in diagram
2
of FIG.
1
.
Public telephone companies typically sell the capacity on a T1 line on a slot by slot basis, and a user wishing high speed data communication can buy any number of slots. Slots can be aggregated into higher speed channels with the effective channel speed being the combined speed for the number of slots. A standard T1 line can have as many as 24 channels, each having a data rate of 64 Kb/s, or as few as one channel with a data speed of 1.544 Mb/s. A T1 line that is divided into more than one channel is sometimes referred to as “structured line” and a T1 line that carries only one channel is referred to as an “unstructured line.” For example, a company having a main office in San Francisco and a satellite office in Palo Alto, might for example, lease eight T1 slots between the two offices and use four of the slots for four separate voice channels and aggregate the four other slots into a single higher speed data channel. The company would therefore have five channels, four at 64 Kb/s for voice, and one at 0.25 Mb/s for data.
In some areas, phone companies have begun to install a new switching architecture into their central offices for use in CO to CO communication. This technology is referred to as cell-based ATM (Asynchronous Transfer Mode) switching. Cell-based ATM switching is designed to effectively serve the needs of both continuous low-bandwidth digital voice data and bursty high-bandwidth data. At the heart of cell-based switching is the cell, a small unit of data with an address identifying its destination and path through the ATM network. The standardized ATM network protocol employs an cell of 53 bytes, 48 bytes of data and 5 bytes of ATM header. The destination of data on an ATM line is determined by the cell header and not by the slot location within a frame as in TDM. Therefore ATM is said to be asynchronous. ATM data transfer speeds are typically much higher than the speed of a T1 line. A typical ATM line operates at 155 Mb/s, or about 100 times faster than a T1 line.
As telephone and digital system carriers have begun adopting cell-based switching for some parts of communication networks, a need has arisen for connecting existing TDM lines into new cell-based ATM switches. This need has been filled by a device referred to in the art as an SAR Processor (SAR stands for Segmentation and Reassembly). An SAR processor provides an interface between a number of TDM lines and a cell-based ATM switch network. The SAR processor typically accomplishes this by collecting data received on a TDM channel in groups of 47 data bytes, and then putting that data into an ATM cell (which has 48 data bytes) for transmission over an ATM switch. The SAR adds one byte of its own header information to each cell, and in some applications adds an additional one byte of data every eight cells for timing purposes. An ATM cell leaving the SAR therefore contains 47 bytes of TDM data for most cells, with possibly every 8th cell for structured lines containing only 46 bytes.
FIG. 1
illustrates some of these concepts in a block diagram showing a central office
5
having an SAR
10
, connected to an ATM network
20
. As shown in
FIG. 1
, SAR
10
connects to eight T1 or E1 TDM lines
25
at its TDM interface and to one ATM interface line
15
at its ATM interface. Line
15
is one input into ATM network
20
, which may be partly located in CO
5
. In the embodiment shown, when these eight interface lines are E1 lines, they can define as many as 256 independent TDM channels, with up to 32 channels per line, or they can define as few as eight high speed channels, with each TDM line carrying one channel. When lines
25
are T1 lines, they can contain up to 192 channels. The format of data on one T1 line is shown in diagram
2
.
A basic function of SAR
10
is the temporary storing of data received on lines
25
and the scheduling of data out of the ATM interface line
15
. Data is transmitted on line
15
in fixed-width ATM cells at a fixed high speed, and the data rate on the ATM line is typically about 100 times faster that the data rate on any one T1/E1 line. The amount of time it takes to transmit one ATM cell on line
15
is referred to as the ATM cell-time. Data is transmitted on lines
25
on a variable number of channels at various speeds depending on the number of slots allocated to a channel. SAR
10
must buffer this incoming data on various channels until enough data is collected to make an ATM cell (47 bytes) and then must transmit that cell on ATM line
15
. SAR
10
must allocate the data space on line
15
fairly among all the TDM channels to insure that delay is kept to a minimum on each channel.
Deciding from which of the 256 possible TDM channels to send a cell during each ATM cell-time is non-trivial. One of the factors that makes the decision complex is that different types of data carried on different channels may be either very sensitive or very insensitive to different types of delay. One kind of delay of concern is the actual cell delay through an SAR, i.e., how much delay is there between an input bit and the subsequent output of that bit. This delay is referred to as latency. A second and often more important type of delay is j
Chaudhri Imran N.
Holden Brian D.
Lennox Edward
Smedley Richard A.
Smetana Denis A.
Allen Kenneth R.
Kwoh Jasper
Nguyen Chau
PMC-Sierra Inc.
Townsend and Townsend / and Crew LLP
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