Asynchronous bit-table calendar for ATM switch

Details Asynchronous bit-table calendar for ATM switch Asynchronous bit-table calendar for ATM switch

1996-03-15

1998-12-01

Hsu, Alpus H.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370474, H04L 1256

Patent

active

058449019

ABSTRACT:
A segmentation and reassembly processor (10) is disclosed for use in interfacing a group of time-division multiplexed lines (25) to a cell-based communication environment (20). The SAR uses a bit-table calendar (100) to schedule cells to be sent to the cell-based network. A cell service decision circuit (50) reads frame events from a frame advanced FIFO (40) and signals a cell builder (60) to assemble cells of data from a frame buffer (70) for transmission to a cell based output (50).

REFERENCES:
patent: 5301055 (1994-04-01), Bagchi et al.
patent: 5394397 (1995-02-01), Yanagi et al.
patent: 5491691 (1996-02-01), Shtayer et al.
patent: 5533020 (1996-07-01), Byrn et al.
patent: 5563885 (1996-10-01), Witchey
patent: 5572522 (1996-11-01), Calamvokis et al.

Affiliated with

Also associated with

Rating

Asynchronous bit-table calendar for ATM switch does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Asynchronous bit-table calendar for ATM switch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous bit-table calendar for ATM switch will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2401157