Asynchronous bit-serial data receiver

Details Asynchronous bit-serial data receiver Asynchronous bit-serial data receiver

1974-12-18

1976-06-01

Robinson, Thomas A.

Telegraphy

Systems

Line-clearing and circuit maintenance

325321, H04L 524, H04L 700

Patent

active

039611388

ABSTRACT:
The data comprises 8-bit words, plus a leading bit as a start bit at a logic one, and a trailing bit for parity, for a total of 10 bits per group. A synchronizing circuit in the receiver selects a proper phase of clock signals for shifting the data bits into a shift register. An enable flip-flop for the synchronizing circuit is set in response to the start bit at the receiver input, and is reset when the start bit appears in the last bit position of the shift register.
In a preferred embodiment, a clock signal is divided into three phases by a delay line. The synchronizing circuit has three flip-flops for selecting the phase when the enable flip-flop becomes set. These flip-flops enable gates for supplying the selected phase to the shift register. Delays are provided from the transmission line to the shift register and enable flip-flop inputs, so that the sampling is centered over each data bit.

REFERENCES:
patent: 3549804 (1970-12-01), Greenspan et al.
patent: 3582789 (1971-06-01), Mick
patent: 3755748 (1973-08-01), Carlow et al.
patent: 3819853 (1974-06-01), Stein

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