Asynchronous binary array divider

Registers – Transfer mechanism – Traveling pawl

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Details

G06F 754

Patent

active

039566218

ABSTRACT:
This invention comprises an asynchronous binary divider which incorporates a plurality of subtractors connected in such a manner as to shift the difference from one operation to the next. The information flows through the divider with the results appearing at the output without the need for a clock. The divider of this invention uses a plurality of subtractors which receive the divisor and subtract it from the dividend and subsequent remainders. A generated borrow from the most significant digit of the first subtractor indicates whether or not the dividend is larger than the divisor. The individual bits of the remainder generated by the first subtraction are fed to logic circuits comprising a pair of AND gates and an OR gate, and the outputs from the logic circuits determine the values applied to the next row of subtractors. The remainder generated by each successful subtraction is used as the minuend for the next, the divisor is used as the subtrahend for each subtraction and the inverted borrow from the most significant bit of each subtractor serves as the quotient digit in each subtraction row. The remainders at the end of the operation consists of the outputs from the final logic circuits.

REFERENCES:
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patent: 2954168 (1960-09-01), Maddox
patent: 3064896 (1962-11-01), Carroll et al.
patent: 3105897 (1963-10-01), Heijn
patent: 3188453 (1965-06-01), Schneider
patent: 3229079 (1966-01-01), Zink, Jr.
patent: 3257548 (1966-06-01), Fleisher et al.
patent: 3378677 (1968-04-01), Waldecker et al.
patent: 3437801 (1969-04-01), Wilhelm, Jr.

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