Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-08-10
2002-06-11
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S158000, C341S164000, C341S115000
Reexamination Certificate
active
06404372
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to electronic circuits, and more specifically to analog-to-digital (A/D) converters.
BACKGROUND OF THE INVENTION
A converter is an electronic component (often a single chip) employed in an electronic circuit to perform conversions between analog signals and digital data. An analog-to-digital (A/D) converter is used to change an analog signal into digital data having a direct correspondence to the value of the analog signal. Similarly, a digital-to-analog (D/A) converter converts an input of digital data into a corresponding analog signal. Both A/D and D/A converters are used in many types of electronic circuits/devices. For example, an A/D converter is employed in a digital phone to convert a human voice (an analog signal) into digital data that can be transmitted over a digital network. Also, a D/A converter is often used in a modem to convert digital data from a computer into an analog signal suitable for transmission over a non-digital network such as a plain old telephone system (POTS).
Typically, when an A/D converter receives an analog voltage signal at its input, this signal is converted into digital data that includes a binary representation of the level of the signal at the input. The digital data outputted by an A/D converter usually includes a digital word “d” that has n-bits of resolution, where d=b
1
/2
1
+b
2
/2
2
+ . . . +b
n
/2
n
, and where b
1
, b
2
, . . . , b
n
are binary bit coefficients having either a one or a zero value. These bit coefficients are used to create the digital word “d” that is presented at the output of the A/D converter. A parallel A/D converter presents all of the bit coefficients simultaneously at the output and a serial A/D converter provides the bit coefficients serially, i.e., one bit coefficient at a time, at the output.
The digital word output of an A/D converter is only an approximation of an actual analog signal received by the converter. Often, in order to approximate an analog signal more completely, a digital word will be created with a most significant bit (MSB) coefficient and a least significant bit (LSB) coefficient. Ideally, the actual value of an analog data signal will be within +or −½the LSB of the digital word.
There are many problems that can cause an A/D converter to create a relatively inaccurate digital representation of an analog signal input, including: offset error, scale error, nonlinearity, nonmonotonicity and incorrect latching. It is envisioned that a new design for an A/D converter would help to solve these common problems and would also consider many different factors, including among others, accuracy, sampling rate, throughput rate and cost.
SUMMARY OF THE INVENTION
The present invention is directed at addressing the above-mentioned shortcomings, disadvantages and problems, and will be understood by reading and studying the following specifications.
The apparatus and methods described herein convert an analog signal into a digital output. A generator is employed to generate a top voltage boundary and a bottom voltage boundary for a voltage window. A comparator is used to compare the analog input to the top voltage boundary and the bottom voltage boundary for the voltage window. The comparator sets an off state when the analog signal is positioned above the bottom voltage boundary and below the top voltage boundary. The comparator sets an on state when the bottom voltage boundary is greater than the analog input and sets another on state when the top voltage is less than the analog input. Also, a counter is used to increment a digital output when the comparator is in the on state and decrement the digital output when the comparator is in the other on state. The digital output of the counter is latched and represents the value of the analog signal when the comparator is in the off state.
Another aspect of the invention includes an oscillator that generates a control signal that controls the speed that the counter will increment and decrement the digital output. The oscillator is disabled when the comparator is in the off state so that power consumption is reduced. Also, the speed of the counter is slower than the speed that the comparator requires for comparing the analog input to the top voltage boundary and the bottom voltage boundary and setting the state of the comparator in accordance with these comparisons.
Yet another aspect of the invention includes a feed back loop that provides the digital output of the counter to the generator. Also, the top voltage boundary and the bottom voltage boundary are equivalently increased when the counter increments the digital output and equivalently decreased when the counter decrements the digital output. The feedback loop adjusts the position of the voltage window until the original analog signal is within the bounds of the window.
Still another aspect of the invention includes a new voltage window that is generated at a higher position when the counter is incremented and another new voltage window is generated at a lower position when the counter is decremented. A distance between an initial position of the voltage window and the higher position for the new voltage window and another distance between the initial position of the voltage window and the lower position for the other new voltage window being less than the height of each voltage window so that hysteresis is created by the overlap between the bounds of consecutively generated voltage windows. For example, each voltage window could be created 150 milliVolts wide and positioned 100 milliVolts higher than the previous voltage window so that the “extra” 50 milliVolts creates hysteresis between each consecutive window.
Another aspect of the invention includes setting the distance between consecutive voltage windows to be proportional to a constant multiplier of the least significant bit (LSB) of the digital output and less than the height of the adjacent voltage window. Also, an absolute upper limit may be set for incrementing the top voltage boundary and an absolute lower limit can be set for decrementing the bottom voltage boundary for the voltage window.
Yet another aspect of the invention includes a plurality of current sources arranged in an array for the generator. Each current source being separately controlled by a particular bit in the digital output of the counter. The generator including a resistive ladder that is coupled to a plurality of switches that are separately coupled to a corresponding current source in the array. The type of the plurality of switches include an electronic switch and relay. The current sources can be matched or scaled.
Another aspect of the invention includes an n-bit counter that is activated when the analog input to the analog digital device is outside the moving signal window. Another aspect of the invention limits the speed of the n-bit counter in order to stabilize the feedback loop. The n-bit counter only makes one step during the time necessary for the comparators to respond. This moves the voltage window up or down one unit. The voltage window continues moving until the comparators indicate that the analog input is within the window generated, or until the voltage window is at an endpoint. If the window is at the high or low position, the window is reset.
REFERENCES:
patent: 4160243 (1979-07-01), Noriya et al.
patent: 5515050 (1996-05-01), Luedtke
Mai Lam T.
Sullivan Timothy P.
Tokar Michael
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