Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2000-04-03
2002-10-08
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S077000, C327S307000, C327S379000, C326S030000, C326S082000, C326S026000, C330S009000
Reexamination Certificate
active
06462588
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a circuit used with a high-speed bus and, more particularly, to a method and circuit that provides for asymmetric control of an output driver for purposes of calibration.
BACKGROUND
To permit a rapid switching speed on a bus with low signal to noise ratio and good signal integrity, it is desirable for a current mode driver to set and control the current at which the driver operates. An existing system for setting and maintaining the operating current of a current mode driver is designed for use with a master-slave bus architecture. With such a bus architecture, two problems need to be solved to set the correct operating current on the bus: properly set the operating current of the master's current mode drivers, and properly set the operating current of the slave's current mode drivers. The current level of the drivers are initially set and periodically updated to compensate for the voltage offset due to process, voltage, and temperature variations by circuitry in the master and slave devices. The calibrated current mode driver can thus be used on a bus signaling system with multiple transmission lines and current mode drivers. A current control mechanism typically evaluates various voltage levels and increments or decrements a current control counter accordingly to set an appropriate output level.
FIG. 1
illustrates a current calibration mechanism using two of the output drivers and transmission lines on the signal bus. In a first portion of the circuit, a terminating resistor
102
is coupled between a terminating voltage (Vterm) and a bus conductor
104
which includes a matched impedance transmission line on a printed circuit board, an integrated circuit package and a socket. A pad
106
is coupled to bus conductor
104
. Pad
106
is, for example, a conductive pad located on the silicon of the integrated circuit package. Similarly, bus conductor
104
may be a conductor, such as a trace, located on a printed circuit board. An output driver
108
is coupled to pad
106
and to ground. Output driver
108
is off as indicated by the logic “0” applied to the driver. A pass gate
110
is coupled between pad
106
and a resistor
112
, to enable the current calibration process. Resistor
112
is also coupled to a voltage comparator
114
, which is coupled to a current control circuit
116
. Comparator
114
and current control circuit
116
are used to perform current control functions.
A second portion of the circuit shown in
FIG. 1
includes a terminating resistor
118
coupled between a terminating voltage (Vterm) and a bus conductor
120
. A pad
122
is coupled to bus conductor
120
and an output driver
124
. Output driver
124
is on as indicated by the logic “1” applied to the driver, which causes a current flow, indicated by Iol, through the output driver to ground. A pass gate
126
is coupled between pad
122
and a resistor
128
to enable the current calibration process. Resistor
128
is also coupled to resistor
112
and comparator
114
. Resistors
112
and
128
function as a voltage divider. The adjusted result of the current control circuit
116
is then fed back to the output drivers
108
and
124
to update the output current of the drivers.
In many instances, it is desirable for the circuit of
FIG. 1
to balance (i.e., match) the voltage swing such that the voltage amplitude above Vref is equal to the amplitude below Vref. Additionally, during the calibration process, the circuit of
FIG. 1
balances the voltages present in the two different parts of the circuit, such as the voltages indicated by Voh and Vol. When Rh (resistor
112
) equals R
1
(resistor
128
), the circuit balances the voltage such that a midpoint voltage, Vmid, located between the two bus conductors
104
and
120
is approximately midway between the two voltages Voh and Vol. This midpoint voltage, Vmid, is provided to comparator
114
along with a fixed reference voltage, Vref. The output of comparator
114
represents a digital state of the difference between Vmid and Vref. If Vmid is higher than Vref, a logic signal output of 1 is generated to indicate more current is required. If Vmid is lower than Vref, a logic signal output of 0 is generated to indicate less current is required. If Vmid and Vref are equal (the circuit is “balanced”), then the output of comparator
114
will toggle between 1 and 0, indicating no difference between the two voltages. In this situation, the current will be toggling between two levels on opposite sides of the balanced level. Thus, the current flowing through output driver
124
is adjusted until:
Voh
+
Vol
2
=
Vmid
(
which
equals
Vref
)
which indicates that the voltages are balanced (i.e., Vref is midway between Voh and Vol).
Balancing the voltages as described above is desirable if the noise and voltage characteristics are the same for both logic states of the transmitted signal (voltage high for logic state 0 and voltage low for logic state 1 ). Balancing is further desirable if both signal voltage levels have similar noise characteristics or receive other similar effects from other sources (such as inductive ringing). If the noise or other source affects each signal voltage level in approximately the same manner, the circuit continues to balance the two voltage amplitudes (high and low) and the comparator generates the correct value.
However, in other situations, one signal voltage level may receive a noise profile that is not present on the other signal voltage level, or one signal voltage level may receive a stronger noise signal (i.e., higher voltage) than the other signal level. In this situation, a circuit that balances the two voltages of the type discussed above may not function properly because the noise signal is not balanced. Similarly, other forces, such as inductive ringing or voltage attenuation, may affect one signal level more than the second signal level, thereby causing improper operation when used with a circuit that balances the high and low amplitude at the source of the signal transmission line.
An improved circuit described herein addresses these and other problems by allowing for the offset of voltages between the output high voltage and the output low voltage to compensate for unequal noise or other forces affecting the signals on the signal transmission lines.
SUMMARY
The circuit discussed below allows the offsetting of two voltages: an output voltage high (Voh) and an output voltage low (Vol) with respect to a reference voltage Vref. The calibrated current mode driver can be replicated for all signals within the transmission signal bus to compensate for differences in the voltages on the transmission lines caused by voltage disturbances, such as noise, on the transmission lines and Vterm, and asymmetric changes in voltage amplitude due to voltage attenuation.
In one embodiment, a circuit to control signal levels on a transmission channel includes a comparator having a reference voltage input and a current control voltage input. A voltage divider is coupled to the current control voltage input of the comparator. The voltage divider includes multiple loads to divide voltages associated with a first output driver and a second output driver. The voltage divider also includes multiple switches to activate and deactivate associated loads in the voltage divider. A current control circuit is coupled to an output of the comparator. The current control circuit controls signal levels on the transmission channel in response to an output signal received from the comparator.
In another embodiment, a circuit to control signal levels on a transmission channel includes a comparator having a reference voltage input, a current control voltage input, and an offset control input. The offset control input adjusts the voltage offset on the transmission channel. A voltage divider is coupled to the current control voltage input of the comparator. The voltage divider divides voltages associated with a first output driver and a second
Lau Benedict Chung-Kwong
Nguyen Huy M.
Cunningham Terry D.
Lee & Hayes PLLC
Nguyen Long
Rambus Inc.
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