Asymmetrically stressed CMOS FinFET

Details Asymmetrically stressed CMOS FinFET Asymmetrically stressed CMOS FinFET

2008-07-15

2008-07-15

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S213000, C257S288000, C257S347000, C257S350000, C257S351000, C257S368000, C257S369000, C257S629000, C257S649000, C257SE29021

Reexamination Certificate

active

11162660

ABSTRACT:
A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region comprising a N+ polysilicon layer on one side of the channel region and a P+ polysilicon layer on an opposite side of the channel region, thereby, partitioning the fin structure into a first side and a second side, respectively. The channel region is in mechanical tension on the first side and in mechanical compression on the second side. The FinFET may comprise any of a nFET and a pFET, wherein the nFET comprises a N-channel inversion region in the first side, and wherein the pFET comprises a P-channel inversion region in the second side. The CMOS device may further comprise a tensile film and a relaxed film on opposite sides of the fin structure adjacent to the source and drain regions, and an oxide cap layer over the fin structure.

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