Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal
Reexamination Certificate
2002-10-22
2003-11-04
Ngô, Ngân V. (Department: 2814)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
C438S197000, C438S200000, C257S288000, C257S292000
Reexamination Certificate
active
06642076
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a CMOS image sensor device and, more particularly, to a method to form an improved CMOS image sensor with a double-diffused source on the reset transistor.
(2) Description of the Prior Art
CMOS image sensors have many advantages over CCD sensors. For example, CMOS image sensors demonstrate low voltage operation, low power consumption, compatibility with logic circuits, random access, and low cost. As device dimensions shrink to 0.25 microns, shallow trench isolations (STI) are widely used for device isolation. However, crystal defects located at STI corners can create leaky pixels.
Referring now to
FIG. 1
, a conventional CMOS pixel cell
400
is shown in schematic form. The pixel cell
400
comprises a photodiode sensor
408
. The photodiode sensor
408
is reverse biased between the power supply VDD
404
and GROUND
430
such that it will conduct only a small leakage current. However, the photodiode
408
is sensitive to incident light. Light will cause the reverse current to increase.
The CMOS sensor pixel
400
comprises three additional transistors N
1
412
, N
2
416
, and N
3
420
. The first transistor N
1
412
is the reset transistor for the cell
400
. The cell is operated in a cycle. First, the reset transistor N
1
412
is turned ON as shown by the high state of VRST. The node between the photodiode
408
and the reset transistor N
1
412
is the floating node (FN). When the reset transistor N
1
is ON, FN is pulled up to VDD
404
. The photodiode
408
is then fully reverse biased and has the maximum depletion region.
The reset control signal VRST is next forced low to turn OFF the reset transistor N
1
. The photodiode sensor
408
will now react to incident light by generating reverse leakage current. The leakage current will discharge the floating node (FN) as shown. If the pixel is in the presence of a bright light, a large current will be generated by the photo effect. This current will discharge FN at a rate of, for example, about 200 mV/second or more. If the pixel is in the dark, the leakage current generated will discharge FN at a rate of only about 20 mV/second or less.
The FN voltage is coupled to the gate of the source follower transistor N
2
416
. The source of N
2
416
follows the gate voltage FN with a voltage drop. For example, the FN node during reset may be forced to about 2.5 V if VDD is about 3.3 V. In this case, the source of N
2
416
will be about 2.2 V during reset. After the reset transistor N
1
412
is turned OFF, FN begins to drop at a rate that reflects the relative light intensity incident on the pixel
400
photodiode
408
as described above. This voltage is reflected on the source follower node but with a low output resistance such that any additional loading does not affect the operation of the diode. The row selector transistor N
3
420
is used to select a particular row of pixels
400
for sampling. The row selector transistor N
3
420
is turn ON by the VDI signal that is controlled by the sampling circuit, not shown.
In this example case, a constant load I
LOAD
424
is coupled to the pixel output VOUT. If the row selector transistor N
3
420
for this pixel
400
is turned ON, then the constant load is coupled to the source follower output such that the FN signal is effectively coupled to the output node VOUT. The difference between a dark condition and a bright light condition on the photodiode
408
can be easily seen. During a sampling operation, the VOUT signal is sampled at a fixed number of milliseconds after the reset transistor N
1
is turned OFF. The sampled voltage VOUT corresponds to the relative light intensity. It may be used, therefore, to scan an image by combining the samples of a large array of pixels.
Referring now to
FIG. 2
, a cross sectional view of a part of the pixel structure is shown. The photodiode is formed by the n-well (NW) region
16
and the p-substrate (PSUB)
10
. The NW
16
forms a first terminal of the p-n diode while the PSUB
10
forms a second terminal. Under reverse bias, a depletion region forms between NW
16
and PSUB
10
. The photoelectric current is generated as light photons interact within this depletion region. Two MOS transistors
66
and
70
are also shown in the cross section. One transistor
66
has the source region
38
formed in the NW
16
terminal of the photodiode. This transistor
66
is the reset transistor for the pixel cell.
Shallow trench isolation (STI) regions
18
are used in this technology to enable very small dimensions as described above. A particular problem may occur in the STI
18
. Defects
62
may form in the STI-semiconductor substrate interface due to manufacturing problems, such as crystal defects, material stress, poor trench etching or filling, or planarization damage. These defects
62
may occur at the STI interface with the heavily doped source junction
38
of the reset transistor as shown. This will induce leakage current to flow from the source node (FN) to ground.
As discussed above, the current flow from the FN node to ground is used to measure the intensity of incident light. Any additional source of leakage current will adversely affect the performance of the CMOS image sensor. Further, since the STI defects
62
are somewhat random, this leakage current will occur on some pixels but not others. Therefore, the leakage current effect cannot be cancelled out. As a result, pixels that contain a defect
62
will appear to be in the presence of a large, light source even when the pixel is exposed to darkness. Such pixels are called “white pixels” since these locations in the CMOS image pixel array always appear to be “white” regardless of the actual incident image. It is a primary object of the present invention to address the problem of white pixels caused by STI-induced leakage.
Several prior art inventions relate to U.S. Pat. No. 6,347,054 to Wang et al discloses a flash memory cell having a double-diffused region and a single-diffused region. U.S. Pat. No. 6,323,054 to Yaung et al teaches a method to form an image sensor cell. The photo diode comprises a lateral p-n diode with a space between the p-n regions. Conventional, single-diffused source/drain regions are used in the reset transistor. U.S. Pat. No. 6,306,678 to Chiang et al describes a method to form a CMOS image sensor. A photoresist layer is used to protect a previously formed, photodiode element during the sidewall spacer etch on the transfer transistor gate. Conventional, single-diffused sources and drains having lightly doped drain (LDD) extensions are taught. U.S. Pat. No. 6,194,258 to Wuu teaches a method to selectively form silicide in a CMOS image sensor process. Silicide is formed on the logic-type CMOS transistors. However, a layer blocks formation of silicide in the image cell. The reset transistor uses conventional, single-diffused source/drain regions with LDD.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable CMOS image sensor device and method of formation.
A further object of the present invention is to provide a method to form a CMOS image sensor device with reduced occurrence of the white pixel effect.
A yet further object of the present invention is to form a CMOS image sensor where a double diffused source is used to reduce leakage on the floating node.
A yet further object of the present invention is to form the double diffused source selectively only on the floating node and not on other drain or source nodes in the pixel.
Another further object of the present invention is to provide a CMOS image sensor with improved performance having an improved source region.
In accordance with the objects of this invention, a method to form CMOS image sensors in the manufacture of an integrated circuit device is achieved. The method comprises providing a semiconductor substrate. Sensor diodes are formed in the semiconductor substrate with each diode comprising a first terminal and a second terminal. Gates are formed for transis
Chien Ho-Ching
Tseng Chien-Hsien
Wuu Shou-Gwo
Yaung Dun-Nian
Ackerman Stephen B.
Doan Theresa T.
Ngo Ngan V.
Saile George O.
Schnabel Douglas R.
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