Asymmetrical pulsive delay network

Details Asymmetrical pulsive delay network Asymmetrical pulsive delay network

1997-07-25

2000-04-04

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327264, 327288, H03H 1126

Patent

active

060466197

ABSTRACT:
This invention relates to an asymmetrical delay network connected between first and second voltage references and having an input terminal for receiving a trigger signal, and an output terminal. The network is of the type which includes at least one charge control transistor and at least one delay capacitor, connected in series with each other between the first and second voltage references. In particular, the charge control transistor has a control terminal connected to a generator of a constant current, and the output terminal delivers a delay signal which is synchronized to a first edge of the trigger signal. The invention also concerns a constant pulse generator including at least a first and a second of such asymmetrical delay networks.

REFERENCES:
patent: 4843265 (1989-06-01), Jiang
patent: 5130582 (1992-07-01), Ishihara et al.
patent: 5300837 (1994-04-01), Fischer
patent: 5610546 (1997-03-01), Carbou et al.

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