Fishing – trapping – and vermin destroying
Patent
1996-10-01
1998-07-21
Niebling, John
Fishing, trapping, and vermin destroying
437 41, 437186, H01L 21265, H01L 2144
Patent
active
057834580
ABSTRACT:
Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current-a desirable outcome for high speed circuits.
REFERENCES:
patent: 4272881 (1981-06-01), Angle
patent: 4962054 (1990-10-01), Shikata
patent: 5200358 (1993-04-01), Bollinger et al.
patent: 5296398 (1994-03-01), Noda
patent: 5525552 (1996-06-01), Huang
patent: 5547885 (1996-08-01), Ogoh
Dawson Robert
Hause Fred N.
Kadosh Daniel
Advanced Micro Devices , Inc.
Daffer Kevin L.
Lebentritt Michael S.
Niebling John
LandOfFree
Asymmetrical p-channel transistor having nitrided oxide patterne does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Asymmetrical p-channel transistor having nitrided oxide patterne, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asymmetrical p-channel transistor having nitrided oxide patterne will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1646324