Asymmetrical p-channel transistor having a boron migration barri

Details Asymmetrical p-channel transistor having a boron migration barri Asymmetrical p-channel transistor having a boron migration barri

1996-10-01

1998-04-28

Niebling, John

Fishing, trapping, and vermin destroying

437 41AS, 437 41RL, 437 46, H01L 21265

Patent

active

057443718

ABSTRACT:
Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.

REFERENCES:
patent: 4914046 (1990-04-01), Tobin
patent: 5393676 (1995-02-01), Anjum
patent: 5397715 (1995-03-01), Miller

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