Asymmetrical non-volatile memory cell, arrays and methods for fa

Details Asymmetrical non-volatile memory cell, arrays and methods for fa Asymmetrical non-volatile memory cell, arrays and methods for fa

1993-01-06

1997-03-18

Yoo, Do Hyun

Static information storage and retrieval

Floating gate

Particular biasing

36518514, 257315, 257344, G11C 1300

Patent

active

056129149

ABSTRACT:
A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).

REFERENCES:
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patent: 5053841 (1991-10-01), Miyakawa et al.
D. L. Geriach et al., "Reliability Failure Mechanisms", 1990 International Electron Devices and Materials Symposium, Nov. 14-16, 1990, pp. 273-280.

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