Asymmetrical multiprocessor system

Details Asymmetrical multiprocessor system Asymmetrical multiprocessor system

1976-12-27

1978-02-28

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 1516, G06F 1520

Patent

active

040770605

ABSTRACT:
An asymmetrical multiprocessor system has a main storage or macroprocessor connected under control of a microprocessor for initiation and termination of operation of the macroprocessor. The macroprocessor after being started by the microprocessor runs until a check condition in the macroprocessor occurs, a non-executable operation code (OP code) in the macroprocessor is encountered, or the microprocessor wants control. When the macroprocessor stops the microprocessor is interrupted. The interrupt routine handles the condition causing the interrupt and restarts the macroprocessor. Non-executable OP codes include supervisor call and invalid OP codes. I/O operations are handled by the supervisor call instruction.

REFERENCES:
patent: 3229260 (1966-01-01), Falkoff
patent: 3444525 (1969-05-01), Barlow et al.
patent: 3566358 (1971-02-01), Hasbrouck
patent: 3668650 (1972-06-01), Wang
patent: 3766532 (1972-10-01), Liebel, Jr.

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