Asymmetrical memory cell arrangement

Details Asymmetrical memory cell arrangement Asymmetrical memory cell arrangement

1975-12-22

1977-07-12

Fears, Terrell W.

Communications: electrical

Digital comparator systems

340173FF, 307238, G11C 1140

Patent

active

040357848

ABSTRACT:
A memory cell is provided which comprises a word line, a current source line, a pair of bit lines, a first transistor having a base terminal, a collector terminal coupled to the word line, a first emitter coupled to a first of the pair of bit lines, a second emitter coupled to the current source line, a second transistor having a base terminal coupled to the collector terminal of the first transistor, a collector terminal coupled to the word line and to the base of the first transistor, a first emitter coupled to a second of the pair of bit lines, and a second emitter coupled to the current source line, and means for directing more current through the second transistor than through the first transistor.

REFERENCES:
patent: 3801967 (1974-04-01), Berger

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