Asymmetrical digital subscriber line (ADSL) block encoder circui

Details Asymmetrical digital subscriber line (ADSL) block encoder circui Asymmetrical digital subscriber line (ADSL) block encoder circui

1997-05-01

1999-03-16

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

058839070

ABSTRACT:
A method and apparatus for performing block encoding in an asymmetrical digital subscriber line (ADSL) system uses a pipelined structure. The parity check circuit (116) contains a plurality of pipeline stages (201, 203, 205, and 207). Each stage contains an ADSL input data register (200, 202, 204, and 206) at a beginning of each stage and a carry register (208, 210, and 212) separating each stage. Each stage contains a plurality of carry circuits (214-220) which are serially coupled together by carry signals. The plurality of carry circuits (214-220) use generator polynomial root (.alpha.) processing involving serial carry propagation whereby the pipelining is implemented in the stages (201, 203, 205, and 207) in order to break the serial carry path from one long string to smaller segmented strings which are pipelined together. This pipelining is performed so that parity generation can occur at the higher frequencies required by ADSL systems.

REFERENCES:
patent: 5829007 (1998-10-01), Wise et al.
patent: 5832234 (1998-11-01), Iverson et al.

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