Asymmetrical clock chopper delay circuit

Details Asymmetrical clock chopper delay circuit Asymmetrical clock chopper delay circuit

1988-02-02

1989-07-25

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307292, H03K 3286, H03K 19013

Patent

active

048517119

ABSTRACT:
An asymmetrical delay generator for use in a clock chopping circuit is disclosed. The circuit has a complementary transistor switch memory cell in it. That cell is operated in a mode where one half of the cell operates in saturation mode. That half of the cell controls the pulse width of the chopper. The other half of the cell is not operated in saturation and controls the resetting of the chopper and hence the maximum clock rate at which the circuit will operate.

REFERENCES:
patent: 3165647 (1965-01-01), DeBotiari et al.
patent: 3351784 (1967-11-01), McNulty et al.
patent: 4355245 (1982-10-01), Isugai
IBM Tech. Discl. Bul. vol. 29, No. 7 12/1986 pp. 3148-3151.
IBM Journal by Dorler et al, vol. 25, No. 3, May 1981, pp. 126-134.

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