Asymmetric write-only message queuing architecture

Details Asymmetric write-only message queuing architecture Asymmetric write-only message queuing architecture

1998-12-10

2001-04-03

Shin, Christopher B. (Department: 2782)

Electrical computers and digital processing systems: multicomput

Computer-to-computer data routing

Least weight routing

C710S029000

Reexamination Certificate

active

06212543

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to computer systems. More particularly, the present invention relates to message passing to and from input/output (I/O) subsystems within a computer system.
BACKGROUND OF THE INVENTION
Prior art computer system architectures typically assume that each process within the computer system has equal access to shared structures. However, access to shared structures is not equal when one or more processes access a structure via bus or other communications device and other processes access the structure locally. The processes that access the structure locally typically have a much lower cost in terms of latency and overhead than processes that access the same structure via a bus.
Costs in accessing structures across a bus are asymmetric in the sense that write operations can be performed more efficiently than read operations because the device writing data is not required to wait for a response from the device to which data is written. Read operations, however, require that the reading device either wait for data to be returned or halt activity to receive data from the device that is read. When bridges or other devices are involved in a read operation the cost becomes even greater because multiple devices are used in the communications path, which requires multiple access requests and grants.
What is needed is an architecture that passes messages to and from shared structures that takes advantage of the fact that write operations are more efficient that read operations.
SUMMARY OF THE INVENTION
A method and apparatus for asymmetric message queuing is described. A free list is maintained with a first device. A work list indicating data to be processed is maintained with a second device. A head pointer for the work list and a tail pointer for the free list are maintained with the first device. A head pointer for the free list and a tail pointer for the work list are maintained with the second device. In one embodiment, changes to the head pointer for the free list and changes to the tail pointer for the work list are caused by write operations from the second device. In one embodiment, changes to the head pointer for the work list and changes to the tail pointer for the free list are caused by write operations from the first device.


REFERENCES:
patent: 4403285 (1983-09-01), Kikuchi
patent: 4908750 (1990-03-01), Jablow
patent: 5430874 (1995-07-01), Kumazaki et al.
patent: 5708660 (1998-01-01), Riedel
patent: 5838915 (1998-11-01), Klausmeier et al.
patent: 5925099 (1999-07-01), Futral et al.
patent: 5987031 (1999-11-01), Miller et al.
patent: 5987580 (1999-11-01), Jasuja et al.
patent: 5999980 (1999-12-01), Tanaka et al.

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