Asymmetric virtual ground p-channel flash cell with latid n-type

Details Asymmetric virtual ground p-channel flash cell with latid n-type Asymmetric virtual ground p-channel flash cell with latid n-type

1997-03-05

1998-10-13

Fears, Terrell W.

Static information storage and retrieval

Floating gate

3651851, G11C 1300

Patent

active

058222421

ABSTRACT:
A memory cell having an asymmetric source and drain connection to virtual ground bit-lines providing an abrupt junction suitable for band-to-band hot electron generation and a gradual junction suitable for Fowler-Nordheim tunneling on each side of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a semiconductor substrate having a first conductivity type; (3) forming a dielectric covering a semiconductor substrate; (3) forming a first and second column of floating gate cores on the dielectric; (4) implanting a first dopant along a first dopant strip, the first dopant strip aligned between the first and second column and having a second conductivity type opposite the first conductivity type; (5) implanting a second dopant in a second dopant strip aligned with the first diffusion and extending below the second column, the second dopant having an enhancement of the first conductivity type; and (6) completing formation of control gate dielectric and control gates. The presence of asymmetric source and drain diffusions formed thereby improve the isolation between adjacent memory cells and minimizes the disturb problem.

REFERENCES:
patent: 5452250 (1995-09-01), Riggio, Jr.

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