Asymmetric virtual ground EPROM cell and fabrication method

Details Asymmetric virtual ground EPROM cell and fabrication method Asymmetric virtual ground EPROM cell and fabrication method

1990-06-29

1991-07-16

Hille, Rolf

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 90, 357 91, 357 89, 365185, H01L 2968, G11C 1134

Patent

active

050328816

ABSTRACT:
An array of asymmetric electrically programmable, read only memory (EPROM) cells is formed in a P- semiconductor substrate. The EPROM cells are virtual ground cells, in that there are no fixed connections in the array to ground potential. Parallel bit lines, comprising N+ substrate regions, form the drain and source regions of parallel columns of MOS transistor devices. Each EPROM cell has a floating gate formed on a first polysilicon layer, and a control gate formed on a second polysilicon layer. Each bit line has two lateral edge regions. An N- implant region overlaps one lateral edge region of each bit line, thereby forming a graduated PN junction between the drain and channel of each MOS transistor device. This substantially prevents hot electron generation by the drain and enables one cell to be programmed without programming of its nearest neighboring cell. A second P- implant region overlaps the other lateral edge region of each bit line, forming a sharp PN junction between the source and channel of each adjacent MOS transistor device, thereby enhancing hot electron generation, which makes the programming of cells more efficient.

REFERENCES:
patent: 4376947 (1983-03-01), Chiu et al.
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4930105 (1990-05-01), Matsumoto et al.
Yoshikawa et al., "An Asymmetrical Lightly Doped Source Cell . . . ", IEEE Transactions on Electron Devices, vol. 37, No. 4, Apr. 1990, pp. 1046-1051.
Chu et al., "The Effect of Trench-Gate-Oxide Structure on EPROM Device Operation", IEEE Electron Device Letters, vol. 9, No. 6, Jun. 1988, pp. 284-286.

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