Asymmetric memory cell

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays

Reexamination Certificate

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C257S335000

Reexamination Certificate

active

06992339

ABSTRACT:
Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

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Ohsawa, Takashi et al., Memory Design Using a One-Transistor Gain Cell on SOI, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, ISSN: 0018-9200, pp. 1510-1522.
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