Asymmetric, double-sided self-aligned silicide

Details Asymmetric, double-sided self-aligned silicide Asymmetric, double-sided self-aligned silicide

2000-09-11

2002-09-24

Picardat, Kevin M. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S412000, C257S413000, C257S756000, C257S757000

Reexamination Certificate

active

06455935

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to fabrication of semiconductor circuit devices. More particularly, the present invention is directed to self-aligned silicide structures and methods of forming the same without excessive consumption of underlying silicon.
2. Description of Related Art
As is well known in processing integrated circuits, electrical contacts must be made among circuit nodes, such as isolated device active regions formed within a single-crystal silicon substrate. As the contact dimensions of devices become smaller, the contact resistance and the sheet resistance of the contacts increase. In this regard, refractory metal silicides have been used for local interconnections to provide low resistance electrical contacts between device active regions within the silicon substrate.
One common method of forming metal silicides is a self-aligned silicide process, often referred to as salicidation. A thin layer of refractory metal, such as titanium, is deposited over a dielectric area and through contact openings formed on the dielectric area to contact underlying silicon circuit elements, such as source and drain active regions formed within a silicon substrate. The structure is generally annealed to form a silicide, such as titanium silicide (predominantly TiSi
2
) at a high temperature. During the anneal, the deposited titanium reacts with the silicon in the contact to form TiSi
2
at the contact openings. Titanium which overlies the dielectric area does not form TiSi
2
, as the titanium does not contact any silicon. The process is referred to as “self-aligned” because the silicide is formed only where the metal layer contacts silicon, for example, through the contact openings. After the first annealing, the unreacted titanium may be removed in a wet etch, and a post-silicidation anneal is performed to lower the sheet resistance of the silicide to acceptable levels. The final annealing converts titanium silicide from the C49 phase to the lower resistance C54 phase. This self-aligned silicide is often referred to by the short form “salicide.”
In the salicidation process, silicon from the contact regions of the substrate diffuses upward into the titanium layer. Similarly, titanium diffuses into the underlying active areas of the silicon substrate. Titanium and silicon react with each other to form a silicide thick enough to provide low sheet resistance. As a result, the doped active area of the silicon substrate becomes thinner due to the consumption of silicon during the reaction. The resultant silicide is said to intrude or sink into the substrate. Over-consumption of the underlying silicon can be problematic for any silicon circuit element, tending to cause voids, and thus device failures. Where contact is made to a shallow junction active area of a silicon substrate, salicide contacts of sufficient thickness cannot be formed without completely destroying a junction.
A need, therefore, exists for an interconnect and method of fabricating the same, which provides the advantages of salicide interconnects without excessive consumption of underlying silicon to which contact is made.
SUMMARY OF THE INVENTION
The aforementioned needs are satisfied by several aspects of the present invention.
In accordance with one aspect of the present invention, a method is provided for forming a self-aligned silicide contact on a silicon substrate. The method includes forming a contact window through an insulating layer over the silicon substrate, thereby exposing a portion of the silicon substrate. A metal nitride layer is deposited over the exposed portion of the silicon substrate. A silicon layer is formed over the metal nitride layer.
In accordance with another aspect of the present invention, a method is provided for forming a metal source layer, which incorporates a uniform distribution of an impurity and a metal, between silicon structures in an integrated circuit. The method includes selecting a sputtering ambient to maximize bulk resistivity for a metal-rich class of layers incorporating the impurity and the metal. A metallic target is sputtered in the selected ambient.
In accordance with another aspect of the present invention, a method is provided for forming a silicide interconnect over a silicon substrate. The method includes selecting a metal layer incorporating an impurity to a level below saturation. The metal layer has a bulk resistivity within about 15% of the maximal resistivity for unsaturated metal layers having the same metal and impurity. The selected layer is deposited over the silicon substrate, and the selected layer and the substrate are sintered.
In accordance with another aspect of the present invention, a method is provided for forming a self-aligned silicide contact to a semiconductor substrate. The method includes opening a contact in an insulating layer to expose an active region of the substrate. A refractory metal source layer is deposited into the contact directly over the active region of the substrate. A silicon source layer is deposited directly over the refractory metal source layer. A silicidation is then performed to form the self-aligned silicide contact. The silicidation preferentially consumes silicon from the silicon source layer as compared to silicon from the substrate in a ratio of greater than about 1.2:1.
In accordance with another aspect of the present invention, an intermediate substrate assembly is provided. The assembly includes a silicon substrate, a metal nitride layer directly over the silicon substrate, and a silicon layer directly over the metal nitride layer. In accordance with a preferred embodiment, this intermediate assembly is sintered to form a silicide contact.
In accordance with another aspect of the present invention, an integrated circuit is provided, including a silicon substrate, an insulating layer formed over the silicon substrate with a contact opening formed in the insulating layer, and a conductive contact directly contacting the silicon substrate within the contact opening. The contact includes metal silicide uniformly interspersed with metal nitride.
In accordance with another aspect of the present invention, an integrated circuit includes a silicon substrate and a self-aligned contact. The contact includes a metal silicide, and the extends into the substrate below the upper surface of the substrate by an amount less than about 30% of the contact thickness.
In accordance with another aspect of the present invention, a self-aligned silicide contact is provided. The contact extends below a substrate surface into a shallow junction transistor active area, which has a junction depth of no more than about 1,000 Å. The contact extends below the substrate surface by no more than about 30% of the junction depth.
These and other features of the present invention will become more fully apparent from the following description and claims.


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Jeong Soo Byun, Hak Nam Kim et al., “Formation of a large grain sized TiN layer using Tinx, the epitaxial continuity at the A1/TiN

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