Asymmetric alignment of substrate interconnect to...

Details Asymmetric alignment of substrate interconnect to... Asymmetric alignment of substrate interconnect to...

2011-04-05

2011-04-05

Pham, Hoai V (Department: 2892)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S128000, C257SE21499

Reexamination Certificate

active

07919354

ABSTRACT:
An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.

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Gary S. Delp, Patent Application entitled: “Base Platforms with Combined ASIC and FPGA Features and Process of Using Same”, U.S. Appl. No. 11/079,439, filed Mar. 14, 2005, pp. 1-22.

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