Associative scalar data cache with write-through capabilities fo

Details Associative scalar data cache with write-through capabilities fo Associative scalar data cache with write-through capabilities fo

1994-12-01

1998-02-10

Chan, Eddie P.

395453, G06F 1208

Patent

active

057178950

ABSTRACT:
Method and apparatus for a scalar data cache in a scalar/vector supercomputer. The scalar data cache comprises a cache array and a cache controller. The cache array comprises a plurality of cache frames; each cache frame comprises a plurality of cache lines; and each cache line comprises a plurality of data words. The cache controller performs a broadside compare of the reference address against all addresses held in the cache, and translates the reference address into a cache-array address. For each cache line, there is a corresponding cache-line validity indication which is set "valid" only when every data word in the cache line contains valid data. A cache-line validity comparator operates to provide a cache-line-hit indication if a data word requested is in a valid cache line. A cache-load controller is described for loading data from a common memory into every data word of a cache line and for marking the cache line "valid". For at least one of the plurality of scalar registers, a cache accessor is described for providing fetch access to the data words in the cache array, and for providing write-through-cache capability to the data words in the cache array.

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European Search Report for International Application No. PCT/US 95/ 09936 completed on Nov. 30, 1995 by Examiner R. Weber, 2 pages.

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