Associative memory system for performing hit judgment on cache d

Details Associative memory system for performing hit judgment on cache d Associative memory system for performing hit judgment on cache d

1992-12-16

1995-10-10

Rudolph, Rebecca L.

Boots, shoes, and leggings

364DIG1, 3642531, 395413, 365 49, G06F 1202

Patent

active

054577888

ABSTRACT:
An associative memory system using an associative memory circuit, capable of performing hit judgment on cache data at a high speed. The associative memory system comprises a virtual-address holding CAM circuit 2 for outputting a hit signal 5 when the data previously stored in a supplied address coincides with a supplied virtual address 4, a cache-tag memory circuit 1 for outputting cache-tag data coinciding with the supplied virtual address 4 when the data is present, and a physical-address holding CAM circuit 3 which connects with an output line for outputting the hit signal 5 given from the CAM circuit 2 and outputs the hit signal 6 when a physical address previously stored in the memory area from which the hit signal is outputted coincides with cache tag data supplied from the cache-tag memory circuit 1.

REFERENCES:
patent: 5133058 (1992-07-01), Jensen
patent: 5173872 (1992-12-01), Crawford et al.
patent: 5182799 (1993-01-01), Tamura et al.
patent: 5249276 (1993-09-01), Honmura et al.
"2.6 Gbyte/sec Bandwidth Cache/TLB Macro for High-Performance RISK Processor," IEEEE 1991 Custom Integrated Circuits Conference, pp. 10.2.1 to 10.2.4, May 12-15, 1991, Toshinari Takayanagi, et al.
"An In-Cache Address Translation Mechanism," 13th Annual International Symposium on Computer Architecture, Jun. 2-5, 1986, David A. Wood, et al.

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