Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
1999-10-28
2003-11-25
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S215000, C712S218000, C712S227000, C712S209000, C712S210000, C712S244000
Reexamination Certificate
active
06654869
ABSTRACT:
BACKGROUND
1. Field of the Present Invention
The present invention is related to the field of superscalar microprocessors, and more particularly to a processor that utilizes instruction groups to improve performance and includes facilities for handling exceptions generated by instructions within the groups.
2. History of Related Art
Turning now to the drawings,
FIG. 1
is a simplified block diagram of a processor
100
according to one embodiment of the present invention. Processor
100
as depicted in
FIG. 1
includes an instruction fetch unit
102
suitable for generating an address of the next instruction to be fetched. The fetched instruction address generated by fetch unit
102
is loaded into a next instruction address latch
104
and provided to an instruction cache
110
. Fetch unit
102
further includes branch prediction logic
106
. As its name suggests, branch prediction logic
106
is adapted to make an informed prediction of the outcome of a decision that affects the program execution flow. The ability to correctly predict branch decisions is a significant factor in the overall ability of processor
100
to achieve improved performance by executing instructions speculatively and out-of-order. The address produced by fetch unit
102
is provided to an instruction cache
110
, which contains a subset of the contents of system memory in a high speed storage facility. If the address instruction generated by fetch unit
102
corresponds to a system memory location that is currently replicated in instruction cache
110
, instruction cache
110
forwards the corresponding instruction to cracking logic
112
. If the instruction corresponding to the instruction address generated by fetch unit
102
does not currently reside in instruction cache
110
, the contents of instruction cache
110
must be updated with the contents of the appropriate locations in system memory before the instruction can be forwarded to cracking logic
112
.
SUMMARY OF THE INVENTION
The problems identified above are addressed by a microprocessor and an associated
10
method of operation. The processor includes a fetch unit, an instruction cracking unit, and dispatch and completion control logic. The fetch unit is configured to retrieve a set of instructions from an instruction cache. The instruction cracking unit is configured to receive the set of fetched instructions and adapted to organize the set of instructions into an instruction group. The dispatch and completion logic is adapted to assign a group tag to the instruction group and record the group tag in an entry of the completion table for tracking the completion status of the instructions comprising the instruction group. In one embodiment, the set of fetched instructions are formatted according to a first instruction format and wherein the method further comprises modifying the format of the fetched instructions to a second instruction format prior to execution, where the width of the second instruction format is wider than the width of the first instruction format. In one embodiment, the cracking unit is adapted to break down complex instructions in the set of fetched instructions into multiple simple instructions in an instruction group. In one embodiment, the cracking unit is adapted to break down a load multiple instruction into a set of simple instructions spanning multiple instruction groups. In one embodiment, the cracking unit is adapted to reserve the last entry in the instruction group for instructions with a high exception probability such as a branch instruction. In one embodiment, the dispatch and control logic is adapted to record a single instruction address in the completion table entry corresponding to the each instruction group. Preferably, the single instruction address is the instruction address of the first instruction in the instruction group. In one embodiment, the processor is configured to flush the instruction group in response to detecting an exception generated by an instruction in the instruction group. Preferably, the processor is further configure to disable the group organization facility of the cracking unit prior to reissuing the flushed instructions in response to determining that the exception was generated by an instruction occupying an interior slot in the instruction group .
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patent: 5404557 (1995-04-01), Yamashita
patent: 5826055 (1998-10-01), Wang et al.
patent: 5896519 (1999-04-01), Worrell
patent: 5925124 (1999-07-01), Hilgendorf et al.
patent: 5930491 (1999-07-01), Hilgendorf et al.
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patent: 6324640 (2001-11-01), Le et al.
patent: 454985 (1991-11-01), None
patent: WO 98/06042 (1998-02-01), None
Kahle James Allan
Le Hung Qui
Moore Charles Roberts
Ellis Richard L.
Emile Volel
International Business Machines - Corporation
Lally Joseph P.
Meonske Tonia L.
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