Assessing plasma induced gate dielectric degradation with stress

Details Assessing plasma induced gate dielectric degradation with stress Assessing plasma induced gate dielectric degradation with stress

1997-09-05

2000-03-28

Bowers, Charles

Semiconductor device manufacturing: process

With measuring or testing

438 17, H01L 2166

Patent

active

060431024

ABSTRACT:
Plasma induced degradation of thin gate dielectric layers, e.g., silicon dioxide layers of less than 50 .ANG., is assessed by impressing a constant current density across the gate dielectric layer and measuring the resulting stress induced leakage current as a function of time. The sensitivity of the stress induced leakage current to traps generated in a thin gate dielectric layer enables the use of stress induced leakage current measurements to monitor plasma induced damage during various phases of semiconductor manufacturing.

REFERENCES:
patent: 5600578 (1997-02-01), Fang et al.
K. Naruke, S. Taguchi and M. Wada, "Stress Induced Leakage CUrrent Limiting to Scale Down EEPROM Tunnel Oxide Thickness", IEMD 88, p424-427, 1988.
Piero Olvio, Thao N. Nguyen and Bruno Ricco, "High-Field-Induced Degradation in Ultr-Thin SiO.sub.2 Films", IEEE Transactions on Electron Devices, vol. 35, No. 12, Dec. 1988.
K. Eriguchi, T. Yamada, Y. Kosaka and M. Niwa, "Impacts of Plasma Process-Induced Damage on Ultra-Thin Gate Oxide Reliability", IEEE 0-7803-3575, Sep. 1997.
Hyungcheol Shin and Chenming Hu, "Monitoring Plasma-Process Induced Damage in Thin Oxide", IEEE Transactions on semiconductor Manufacturing, vol. 6, No. 2, May 1993.
"Process Induced Oxide Damage and its Implications to Device Reliability of Submicron Transistors," IEEE/IRPS 1993, pp. 293-296.

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