Assembly queue for a floating point unit

Details Assembly queue for a floating point unit Assembly queue for a floating point unit

1997-03-19

1998-10-27

Treat, William M.

395386, 395387, 395388, 395389, 39580023, G06F 9302

Patent

active

058288732

ABSTRACT:
A microprocessor implements a hierarchical microcode implementation for floating point instructions. Floating point instructions are classified as microcode instructions. The microcode unit parses the floating point instructions into one or more floating point operations and one or more integer operations such as memory load operations. The floating point operations are conveyed to the floating point unit. The memory load operations load the floating point operands of the floating point operations. Floating point operands that are wider than integer operands are handled by multiple memory load operations. Each memory load operation loads a portion of the floating point operand. The portions of the floating point operand are combined is a queue in the floating point unit. When the floating point unit has received the floating point operation and the memory operands that comprise with the floating point operand, the floating point unit dispatches the floating point instruction for execution. Floating point instructions that are too complex to be completed in one pass through the floating point execution pipeline are further parsed into a plurality of floating point operations by the floating point unit.

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