Assembly of plurality of semiconductor devices

Details Assembly of plurality of semiconductor devices Assembly of plurality of semiconductor devices

2001-07-09

2002-08-13

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S666000, C257S676000, C257S692000, C257S723000, C257S737000, C257S738000, C361S735000, C361S784000, C361S790000

Reexamination Certificate

active

06433415

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the invention
The invention relates to semiconductor devices and, in particular, to a novel assembly, of unit semiconductor devices, useful for the miniaturization of electronic appliances.
2. Description of the Related Art
An electronic appliance may comprise a semiconductor device or devices having a variety of functions. The semiconductor device or devices are mounted on a mounting substrate, such as a mother board, and are required to be mounted at an increasingly high density with a recent trend toward miniaturization of electronic appliances.
As a technique expected to fulfill this need, a three-dimensional mounting technique, in which a plurality of semiconductor devices, formed by encapsulating a semiconductor chip with a resin, are stacked, is known. According to this technique, a mounting substrate can gain an extra space in proportion to the number of stacked devices, and can occupy a reduced area accordingly. This may largely contribute to the miniaturization of electronic appliances.
Nevertheless, the three-dimensional mounting technique of the prior art suffers from difficulty in stacking semiconductor devices in the direction of thickness of a mounting substrate, and has not been practical.
SUMMARY OF THE INVENTION
The invention is directed at providing a novel assembly of semiconductor devices, which is useful for the miniaturization of electronic appliances, and is different from those of prior art.
According to the invention, there is provided an assembly of semiconductor devices, wherein the semiconductor device comprises a semiconductor chip and a flexible base, the semiconductor chip being provided with lead-out electrodes on one side thereof for electrical connection with an external circuit, and the flexible base comprising an insulation film and a conductor pattern, the insulation film having an inner opening and outer openings arranged outside the inner opening, and the conductor pattern being located on one side of the insulation film, and comprising a plurality of pairs of an inner lead and an outer lead, the inner and outer leads in each pair being connected with each other, the inner lead having an end extending to the inner opening of the insulation film and being exposed therein, and the outer leads being positioned so as to bridge the outer opening of the insulation film and being exposed therein; and the semiconductor chip being mounted on the flexible base by bonding the lead-out electrodes thereof to the ends of inner leads exposed in the inner opening of the insulation base, and wherein the semiconductor devices are assembled to be connected with each other through the outer leads of semiconductor devices which are adjacent to each other, and-the semiconductor chip or chips, which face a substrate on which the assembly is to be mounted, have external connection electrodes, on which an external connection terminal for mounting is provided.
In a first embodiment, the assembly of semiconductor devices of the invention comprises a stack of semiconductor devices.
In a second embodiment, the assembly of semiconductor devices of the invention comprises semiconductor devices arranged in a plane.
Preferably, the flexible base has an insulation film of polyimide and a conductor pattern of copper or copper alloy.
Preferably, the outer lead of the conductor pattern has a larger width than the width of the inner lead of the conductor pattern.
Preferably, the outer leads of semiconductor devices which are adjacent to each other are bonded together by solder.
More preferably, a metal layer-enhancing the wettability of the outer lead by a solder material is provided on the outer leads of the semiconductor device. For this purpose, the outer leads of the semiconductor device may be provided thereon with a layer of aluminum, a layer of gold, a combination of layers of aluminum and silver, a combination of layers of aluminum and gold, a combination of layers of nickel and gold, or a combination of layers of nickel and palladium.
Preferably, the outer leads of semiconductor devices which are adjacent to each other are bonded together by use of an anisotropic conductive film.


REFERENCES:
patent: 6239496 (2001-05-01), Asada
patent: A-6-268101 (1994-09-01), None

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