Liquid crystal cells – elements and systems – Particular structure – Interconnection of plural cells in parallel
Reexamination Certificate
1998-01-15
2001-06-19
Malinowski, Walter J. (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Interconnection of plural cells in parallel
Reexamination Certificate
active
06249329
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to flat-panel displays (FPDs) and, more particularly, to assembling and sealing large FPDs from a plurality of smaller FPDs (tiles) by using either partial, FPD subassemblies (h-tiles), or unsealed, FPD subassemblies (s-tiles).
BACKGROUND OF THE INVENTION
FPD tiles generally consist of a structure that is disposed between and includes two parallel glass plates. Tiled FPDs are formed from a plurality of tiles that are sandwiched between a cover plate and a backplate. Tiling has been discussed in detail in the previous patent applications bearing Ser. No. 08/571,208, 08/593,759, and 08/652,032, all of which are hereby incorporated by reference; most examples therein reference active-matrix, liquid-crystal display (AMLCD) designs, although many of the concepts and claims are applicable to super twisted nematic LCDs (STNLCDs) and other FPD technologies, e.g., field-emission displays (FEDs), plasmna flat-panel displays (PFPDs) and electroluminescent displays (ELDs).
Two types of tile subassemblies are considered in the instant application. The first type employs only the bottom substrate of an FPD tile. In this design, the cover plate of the mosaic becomes a common, top plate which includes elements to provide functions for all of the tile subassemblies, i.e., masks, screens, electrodes, phosphors, color filters and polarizers. This type of subassembly is called a half-tile or an “h-tile”. H-tiles use only one plate; the usual functions of the second plate are performed on a cover plate that is common to the plurality of h-tiles. The second type of subassembly, called an “s-tile”, uses an essentially complete, small FPD, but it has no seal. In other words, s-tiles are similar to fully-formed tiles, except that they are not sealed at this level of assembly.
In tiled FPDs, a seam is disposed between the boundaries of adjacent tiles, s-tiles or h-tiles. A design-and-assembly technique is generally used that will provide for the manufacture of large displays from a plurality of tiles, including s-tiles or h-tiles, with seams at the boundaries thereof that are not visible to the human eye under intended viewing conditions. A level of hermeticity is used for the AMLCD that is sufficient to inhibit the degradation of the liquid-crystal material. A higher level of hermeticity for PFPDs is necessary, in order to maintain the purity of the inert gas supporting the plasma. An even higher level of vacuum is employed for FEDs, in order to preclude contamination of emitter-electrodes.
Co-pending U.S. patent applications, Ser. Nos. 08/571,208 and 08/593,759 (filed Dec. 12, 1995, and Jan. 29, 1996, respectively), teach methods for fabricating and sealing tiled, active-matrix, liquid-crystal displays in FPD formats, while maintaining optically imperceptible seamlessness between abutting tiles. Although the teachings of these patent applications may also be applied to other FPD designs (e.g., FEDs, PFPDs, ELDs), due to their nature, various other designs and manufacturing techniques are also feasible, as discussed hereinbelow.
In the case of both FEDs and some PFPD designs, light is emitted from the phosphor that is near the top of the optical stack, so that there are fewer reflections from the side walls of these tiled FEDS and PFPDs than there are in AMLCDs, which are back-lighted. Moreover, the high focal-point in the optical stack makes the view angle superior, when compared with other displays which lack special designs to correct such deficiencies. Because of these superior, optical-design factors, it is expected that tiling designs with FEDs will meet the requirements for seamlessness much more easily than other, alternative, FPD technologies. For example, since the lighting efficiency of FEDs may be quite high, substantial masking can be used in both the seam and the pixel perimeter areas, and a screen to counteract reflections from the seams.
A common problem in the manufacture of large FPDs is the relatively low yield therefrom. Yield has been found to be approximately inversely proportional to the FPD area. It is often preferable, therefore, to construct a large FPD from many small ones, known to be good by appropriate inspection and testing.
On the other hand, the number of required connections increases in proportion to the number of tiles. Thus, assembly and interconnection costs accumulate proportionally to the number of tiles. Furthermore, the probability of a defect in the plurality of tiles integrated into an FPD increases with the number of interconnections made. Therefore, it is important to be able to test and ensure that “known good tiles” are used in the assembly of the FPD. It is also important that there be an economical method of reworking connections to the tiles. For the latter reason alone, it is desirable to assemble s-tiles with their own phosphor screens in proper registration, testing them prior to joining them to the interconnection on a backplate and then sealing them with a cover plate.
Another concern is the problem of committing a large number of tiles to an FPD and then finding the seal to be defective. It would be advantageous to isolate the problems of vacuum integrity and interconnection, and solve them independently.
SUMMARY OF THE INVENTION
In accordance with the present invention, there are provided methods of constructing and sealing s-tiled and h-tiled, flat-panel displays. Sealing designs are described to maintain appropriate vacuum levels for field-emission displays (FEDs), plasma flat-panel displays (PFPDs) and liquid-crystal displays (LCDs). The mosaic of tiles forming a flat-panel display may include subassembly tiles, with each consisting of two, unsealed, substantially parallel plates having a structure disposed between them; these are known as s-tiles. The s-tiles are arranged on a backplate and a cover plate. Non-permeable material may be deposited on each of the two plates, with solderable metal overlaid on the non-permeable material. A metallized, non-permeable spacer/connector is also disposed between the backplate and cover plate for hermetically sealing the perimeter of the display which encloses the array of s-tiles. A set of electrical-interconnection, metal feed-throughs can also be disposed in the non-permeable spacer/connector.
A flat-panel display may also be made up of half-tiles (h-tiles), each including an individual bottom plate, and wherein the mosaic of tiles also has a cover plate that is shared in common with all of the h-tiles. The outer seal may be disposed as described above for s-tiles. This common cover plate integrates functions such as masking, screening, color filtering, polarizing and interconnecting. Also provided in accordance with the invention is a method for testing the seal of the flat-panel display. A simulated cover plate is attached by means of a polymeric seal, so that a structure enclosed between the two plates may be evacuated. When a gas is applied around the display seal, its leakage rate is measured, so as to locate the site of defects.
REFERENCES:
patent: 3861783 (1975-01-01), Dill et al.
patent: 5781258 (1998-07-01), Dabral et al.
patent: 5867236 (1999-02-01), Babuka et al.
Dabral Sanjay
Greene Raymond G.
Koons John P.
Seraphim Donald P.
Yost Boris
Malinowski Walter J.
Rainbow Displays Inc.
Salzman & Levy
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