Assembler system and method for a geometry accelerator

Details Assembler system and method for a geometry accelerator Assembler system and method for a geometry accelerator

1997-05-30

1999-03-30

Tramrnell, James P.

395705, 395500, 395583, G06F 945

Patent

active

058899979

ABSTRACT:
An assembler system enables efficient usage of space in a read only memory (ROM) that permits multiway instruction branching. Source code is analyzed and assembled by the assembler system and the assembler system then efficiently places the instructions in the ROM. The source code includes at least the following elements or an equivalent counterpart thereof: next state statements, nonaligned instructions, align statements, and aligned instructions. Next state statements serve as a flag to separate the various instructions. Nonaligned instructions are defined as those instructions that are nonaddressable by other instructions, i.e., those instructions that are not branched to. Align statements serve as a flag to the assembler system that a plurality k (where k is equal to 2.sup.n and where n is a positive integer) of aligned instructions directly follow in succession. Furthermore, aligned instructions are defined as those that are addressable by a plurality of other instructions, i.e., those instructions that can be branched to by a branch instruction. A branch instruction can be a nonaligned or an aligned instruction. The assembler system is configured to store the nonaligned instructions in the ROM in succession starting with a lowest memory location and moving to higher memory locations. Moreover, the assembler system is configured to store aligned instructions in the ROM in sets of k instructions starting with a highest memory location and moving toward lower memory locations, a lowest location of each set of the ROM being a mathematical multiple of k.

REFERENCES:
patent: 4967375 (1990-10-01), Pelham et al.
patent: 5517611 (1996-05-01), Deering
patent: 5590358 (1996-12-01), Mizrahi-Shalom et al.

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