Aspect ratio independent coating for semiconductor planarization

Details Aspect ratio independent coating for semiconductor planarization Aspect ratio independent coating for semiconductor planarization

1994-06-13

1995-09-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437225, 437228, H01L 21469

Patent

active

054534062

ABSTRACT:
A new method for forming a planarized dielectric layer on a patterned conducting layer was accomplished. The method involves forming a insulating layer over a semiconductor substrate having semiconductor devices formed therein. A metal conducting layer is deposited and then patterned by anisotropically etching. The patterned conducting layer is used to make the electrical connections to the device contact. A barrier insulator is deposited on the patterned conducting layer to keep the conducting layer from coming into contact with the spin-on-glass and eroding. A planar dielectric layer is formed over the patterned conducting layer by coating a first spin-on-glass layer at a constant and low speed and then baking and then a second spin-on-glass layer is coated on the first spin-on-glass layer at a constant and high speed and then cured forming an improved planarized dielectric layer.

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