ASIC routing architecture with variable number of custom masks

Details ASIC routing architecture with variable number of custom masks ASIC routing architecture with variable number of custom masks

2000-12-22

2003-09-02

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Rendering selected devices operable or inoperable

C438S443000

Reexamination Certificate

active

06613611

ABSTRACT:

FIELD OF INVENTION
The present invention generally relates to integrated circuits, and more specifically, to a routing architecture for interconnecting various IC devices to form a customized circuit.
BACKGROUND OF THE INVENTION
ASICs are widely used by electrical design engineers to include specialized circuitry in their designs using only a single chip. The term “ASIC” actually refers to a variety of integrated circuit (IC) styles that vary in degree of customizability, including standard cells, which are completely customizable, and gate arrays, which are partially customizable. As a general rule, the more customization that is required, the more expensive the ASIC will be and the longer the ASIC will take to fabricate and/or customize.
In forming ASICs generally, several layers will be required.
FIG. 1
shows a cross-sectional view of a generic integrated circuit. First, active layers are formed on a semiconductor substrate. The active layers
110
include devices such as transistors and diodes. Most active layer devices are formed independently of one another, i.e., they are not connected to form a circuit. Thus, once active layers
110
are formed, metal layers are formed over the active layers to interconnect the devices, thereby forming a circuit. Several metal layers may be required to completely interconnect the devices to form a useful circuit. Four metal layers, M
1
120
, M
2
130
, M
3
140
and M
4
150
, are shown in FIG.
1
. Of course, different types of ICs may require more or less than four metal layers for circuit interconnection.
In between each metal layer is an insulating layer
115
,
125
,
135
,
145
as shown in FIG.
1
. Insulating layers are present to prevent shorts between metal layers. To interconnect the metal layers, vias
116
are formed through the insulating layers.
In forming the structure of
FIG. 1
, after the active layers
110
are formed, an insulating layer
115
is formed over the active layers
110
, for instance, by growth or deposition of insulating material. Next, a masking step is utilized to form vias in the insulating layer, as is generally known in the art. Such masking often entails depositing a photoresist layer and patterning the layer using ultra-violet light, enabling removal of only selected portions of the photoresist, and then etching the insulating layer in accordance with the photoresist pattern. After forming the vias, a metal layer is deposited and then patterned using a similar masking process, so that metal remains only in desired locations. The process is repeated for each insulating layer and metal layer required to be formed.
Thus each metal layer required to be formed generally demands at least two masking steps: one step to form vias through the insulating layer to connect to the layer below and one step to form connection wires or lines. Unfortunately, each mask step required generally entails significant time and expense.
At the active layer level, ASIC active devices are generally arranged to form an array of function blocks, also commonly referred to as cells or modules. To interconnect active devices within each function block (i.e., form “local interconnections”) a series of horizontal and vertical connection lines formed in the metal layers are utilized. As is well understood in the art, any two points can be connected using a series of horizontal and vertical connection lines. While such local interconnections can be done in one metal layer, more typically, horizontal connections are formed in a first metal layer (M
1
)
120
and vertical connections are formed in a second metal layer (M
2
)
130
with an insulating layer
125
having vias
116
formed between M
1
and M
2
.
As should be understood and as used herein, “horizontal” is meant to describe all metal lines running in a first direction such that all horizontal lines lie substantially parallel to one another. “Vertical” is meant to convey all lines that run in a second direction which is substantially perpendicular to the first (horizontal) direction. Neither “horizontal” nor “vertical” is meant to convey anything more specific than relative position to one another. Moreover, as should be understood by those of skill in the art, horizontal lines and vertical lines are formed in the metal layers which are parallel to the active layer surface. “Horizontal” and “vertical” do not convey lines that are perpendicular to the active layer surface.
The local interconnections within each function block described above are typically quite dense, and often function blocks themselves must be connected together (i.e., circuit “routing”). Yet routing in lower metal layers over function blocks is often impractical due to the large number of obstructions formed by the local interconnections in those lower layers. Therefore, in order to form connections between the function blocks, routing has typically been done “around” the function blocks and will be discussed below with respect to
FIGS. 2-3
.
The Channeled Approach
One function block routing solution is shown in
FIG. 2
, showing a generalized plan view of a standard cell-type ASIC. As shown, in a standard cell, each function block
160
(
160
a
-
160
i
) will have a unique number and arrangement of active devices and will thus vary in horizontal size with respect to one another (although they are typically structured to have the same vertical height). Function blocks
160
are shown with dashed lines to indicate their conceptual formation in active layers
110
. As discussed above and as shown in function block
160
d
, local interconnections within each function block are typically formed by horizontal lines in M
1
, e.g.,
174
,
176
, and vertical lines in M
2
, e.g.,
178
. The horizontal and vertical lines are connected in their respective layers by vias, shown as “dots.” Vias may not only connect M
1
and M
2
to each other but may also connect M
1
and/or M
2
to an active layer.
The function blocks
160
are further formed into rows
170
a
,
170
b
,
170
c
. Each row is separated from one another by a “channel” region
172
a
,
172
b
. The channel region is then used for horizontal routing between function blocks to avoid routing over the function block space. For instance, referring to
FIG. 2
, channel lines
180
-
182
and
184
-
186
are formed in channels
172
a
and
172
b
, respectively, using M
1
. Vertical lines
190
-
199
are formed in M
2
. Vertical lines
190
-
193
are used to couple the active devices in function block
160
d
to channel lines. The channel lines in turn are further connected (in M
2
) to other function blocks, e.g., with vertical lines
194
-
199
. As shown, the channel lines can run the entire length of the channel or can run for a short distance within the channel.
Vias in the function block are connected to channel lines with connector lines that enter from above the function block, e.g., line
192
, from below the function block, e.g., line
193
, or double entry (connected from above and below), e.g., lines
190
,
191
. Lines could also simply “feed-through” the function block with no connection to a via; however, feed-throughs are often impractical because of dense local interconnections within the function blocks, limiting routing flexibility.
Gate arrays, like standard cells, have also used an approach as described above with reference to FIG.
2
. That is, gate arrays have also been fabricated with channels to use for routing between function blocks. In gate arrays, however, the active layers are fixed (non-customizable), having a predefined number and arrangement of active devices in each function block. Thus, while fully-customizable standard cells can customize channel size larger or smaller, in gate arrays the channel size is fixed, further limiting routing flexibility.
In summary, the “channel” technique described with respect to
FIG. 2
, conventionally does all routing among function blocks in the channel regions. The only M
1
metal outside of each function block (i.e., not used for local interconnections) is located in the channel regions, bet

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