ASIC routing architecture

Details ASIC routing architecture ASIC routing architecture

2005-04-26

2005-04-26

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257S208000, C257S211000

Reexamination Certificate

active

06885043

ABSTRACT:
An embodiment of the invention includes a routing architecture with a plurality of predesigned layers and a custom layer. The structure includes a plurality of parallel vertical tracks. In one layer, the tracks include a pin coupled to an input/output of an underlying function block and the track also includes a first portion of an unbroken conductive path. A second portion of the unbroken conductive path is formed under the pin in at least a second predesigned layer. In some embodiments, the second portion of the unbroken conductive path is formed in the second predesigned layer for some tracks and a third predesigned layer for other tracks. Hence, pins and unbroken conductive paths are multiplexed in a single track. In addition, the second predesigned layer further includes long horizontal conductors. When using the predesigned layers, the custom layer can be structured to provide free global routing with distinct local routing, all while using an array structure independent of routing channels and without rendering any function blocks unusable. Moreover, a structure in accordance with the invention includes conductors for clock distribution which can be used to form multiple independent clock domains. The structure is compact, yet flexible and can be customized in some embodiments with 1-2 masks.

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Greg Semeraro, David H. Albonesi, Steven G. Dropsho, Grigorios Magklis, Sandhya Dwarkadas, Michael L. Scott, “Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture,” IEEE Computer Society, pp. 62-68 (Nov.-Dec. 2003).

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