Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1998-11-24
2001-09-11
Kulik, Paul V. (Department: 2177)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S034000, C358S001100
Reexamination Certificate
active
06289436
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a control system and method of an ASIC (application-specific integrated circuit) used with an image formation system and in particular to a control technique of a reset signal in an ASIC for an image formation system.
2. Description of the Related Art
In recent years, image formation systems such as printers, copiers and facsimile machines produce high quality images at high speeds. In such image formation systems, increasingly the tasks of processing the image formation system have been removed from a main CPU and assigned to an ASIC (application-specific integrated circuit) that act as a dedicated coprocessor to the main CPU. The ASIC contains several modules depending on the complexity of the processing flow. Further, several registers are assigned to each module. At the termination of a processing sequence in the ASIC, a specific register needs to be cleared for use in the next processing cycle.
Previously, when a register needs to be cleared, a hardware reset method using an external signal or a software reset method for generating a reset signal by accessing a specific address have been used.
In a hardware reset, if the user stops power supply when voltage falls below a given threshold value, a reset signal is generated by hardware and is supplied to the ASIC from the outside; thereby clearing all the registers in the ASIC.
In the software reset, all the registers in the ASIC can be cleared using a program. A specific register can also be cleared selectively by accessing a specific address.
However, if all the registers in the ASIC are initialized by the hardware or software reset method at the stage of the termination of a processing sequence, registers, buffers, etc., that store data that is required in the next processing is also cleared. In such a case, the registers must be initialized with the same data several times wasting time in the process.
On the other hand, the software reset method allows accessing specific registers as described above. Nevertheless, programming, particularly timing, such a software method is difficult. It also leads to lowering of the processing speed.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an image formation system ASIC control system and method capable of selectively clearing only registers and other data storage units requiring initialization in response to the internal state and external state of an image formation system ASIC. A plurality of signals for resetting predetermined registers and other storage units are provided in the ASIC and are used properly in response to the internal state and external state of the image formation system ASIC.
Thus, the data required for the next processing can be held intact in other data storage sections, so that the data transfer time is shortened. Since a specific data storage section can be selectively cleared according to the provided reset signals, timing design is facilitated and the processing speed in the image formation system does not lower.
To achieve the objectives of the invention there is provided an ASIC control system for an image formation system application-specific integrated circuit (ASIC) comprising a plurality of data storage sections for performing data processing while storing data in the data storage sections, wherein the ASIC control system resets the data storage sections to clear the data stored therein and generates N reset signals, wherein N is an integer equal to or greater than two, for resetting a preselected subset of the plurality of data storage sections.
Preferably the ASIC control system comprises a reset signal generator being installed in the ASIC for generating the N reset signals in response to a change in the internal state of the ASIC.
Still preferably, the reset signal generator comprises an internal reset request generation source for requesting reset responsive to the change in the internal state of the ASIC and a reset signal selector for selecting at least one of the N reset signals based on the reset request from the internal reset request generation source and outputting the selected reset signal to the data storage section corresponding thereto.
Still preferably the internal reset request generation source is a state machine for indicating the internal state of the ASIC.
Further improvements include the ASIC control system further including first external reset request generator being formed of ASIC external hardware for requesting reset of all of the data storage sections.
Preferably the ASIC control system includes a second external reset request generator being formed of ASIC external software for requesting reset of a predetermined one of the data storage sections.
Still preferably the reset signal selector ANDs or ORs an external reset request from the second external reset request generation means and an internal reset request from the internal reset request generation source for outputting a reset signal to the corresponding data storage section.
Another aspect of the present invention is a method for resetting data storage section to clear data stored therein for controlling an ASIC in an image formation system ASIC comprising a plurality of data storage sections for performing data processing while storing predetermined data in the data storage sections, wherein N reset signals for resetting a preselected subset of the data storage sections are used properly in response to an internal state and an external state of the image formation system ASIC, wherein N is an integer greater than 2.
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Kulik Paul V.
Seiko Epson Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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