Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2001-02-26
2003-09-02
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185190
Reexamination Certificate
active
06614683
ABSTRACT:
BACKGROUND
The present invention relates generally to memory devices. More particularly, the present invention relates to an ascending staircase read technique for a multi-level cell NAND flash memory device.
A variety of semiconductor memory devices have been developed for storage of information. Examples include volatile and nonvolatile memory. Nonvolatile memory provides a key advantage in that it retains stored data after power is removed from the device. One example of nonvolatile memory is flash memory. However, manufacture and operation of nonvolatile memory is generally more complex than for volatile memory. For all memory devices, important design goals are increased storage density and reduced read and write times.
A conventional memory device includes an array of storage cells memory cells. Each cell stores a single binary digit or bit of information. For example, in a flash memory, the threshold voltage of a transistor in the memory cell is adjusted according to the data stored. During a read cycle, the threshold voltage is sensed to resolved the state of the data stored. In a conventional binary memory, this data is conventionally described as having a state of logic 0 or logic 1. The array of storage cells is surrounded by circuits for reading and writing data and controlling operation of the memory device.
Recently, multi-level cells have been developed. Multi-level storage refers to the ability of a single memory cell to store or represent more than a single bit of data. A multi-level cell may store 2, 4, 8 . . . etc., bits in a single storage location.
Multi-level cell devices provide a substantial advantage by exponentially increasing the storage capacity of a memory device. However, multi-level cell devices present several challenges for developing circuit designs to access the memory cells. One such challenge is reliably and rapidly reading the data stored in a multi-level storage cell.
BRIEF SUMMARY
By way of introduction only, a method for resolving data to one stored level of N possible stored levels in a multi-level memory includes receiving an access address associated with a memory location of the multi-level memory and applying an ascending staircase read voltage to a word line associated with the access address. The method further includes detecting a sense signal produced on a sense line associated with the access address in response to the stored level and a value of the staircase read voltage, for each value of the ascending staircase read voltage, storing data responsive to the sense signal, and after application of a final value of the ascending staircase read voltage, producing an N-bit value corresponding to the one stored level stored in the memory location.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the following claims, which define the scope of the invention.
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Phan Trong
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