Artificial neural network implementation

Details Artificial neural network implementation Artificial neural network implementation

1988-10-27

1990-08-21

Smith, Jerry

Boots, shoes, and leggings

307201, 364513, G06C 712, G06C 7163

Patent

active

049512390

ABSTRACT:
An artificial neural network having analog circuits for simultaneous parallel processing using individually variable synaptic input weights. The processing is implemented with a circuit adapted to vary the weight, which may be stored in a metal oxide field effect transistor, for teaching the network by addressing from outside the network or for Hebbian or delta rule learning by the network itself.

REFERENCES:
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patent: 3950733 (1976-04-01), Cooper et al.
patent: 4773024 (1988-09-01), Faggin et al.
Goser, K. et al., "Intelligent Memories in VLSI", Information Sciences 34 lsevier), pp. 61-82, 1984.
Wang, S., "On the I-V Characteristics of Floating-Gate MOS Transistors", IEEE Trans. on Electron Devices, vol. ED-26, No. 9, Sep. 1979, pp. 1292-1294.
Sage, J. et al., "An Artificial Neural Network Integrated Circuit Based on MNOS/CCD Principles", AIP Conf. Proc. 151-Neural Networks for Computing, pub. by American Institute of Physics, 1986, pp. 381-385.
Bibyk, S. et al., "Issues in Analog VLSI and MOS Techniques for Neural Computing", in Analog VLSI Implementation of Neural Systems, Mead, C. et al., eds., pub. Kluwer Academic, 1989, pp. 103-133.

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