Article for de-embedding parasitics in integrated circuits

Details Article for de-embedding parasitics in integrated circuits Article for de-embedding parasitics in integrated circuits

1999-02-02

2001-04-03

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S630000, C257S652000

Reexamination Certificate

active

06211541

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor testing in general, and, more particularly, to an article that facilitates the de-embedding of parasitics in integrated circuits and that can also be used as a calibration standard for semiconductor test equipment.
BACKGROUND OF THE INVENTION
As is well known in the prior art, integrated circuits formed on semiconductor wafers typically comprise a variety of active and passive components (e.g., transistors, diodes, capacitors, interconnections, etc.). Typically, an integrated circuit is fabricated so that its components exhibit certain physical characteristics in accordance with a design specification, and, therefore, it is desirable to be able to verify that once an integrated circuit is manufactured its components do indeed exhibit the desired characteristics.
Because it is difficult to test an individual component in a typical integrated circuit, exemplars or “stand-alone” copies of the individual components are fabricated on the wafer and are analyzed as representative of the other components. Such analysis by representation is known as “in-process” or “on-chip” testing and is reasonable when the exemplars are fabricated using the same processes and design specifications as their counterparts.
In on-chip processing, the isolated exemplar, which is known as the “device under test” or “DUT,” is electrically connected via leads to contact pads so that the physical characteristics of the DUT can be measured by external testing equipment. Typically, however, the leads to the DUT themselves hinder the measurement of the DUT itself because the leads exhibit physical characteristics that mask or obfuscate the physical characteristics of the DUT. Therefore, in order to accurately measure the physical characteristics of the DUT, the physical characteristics of the leads, which are known as “parasitics,” must be understood so that they can be factored out to reveal the characteristics of the DUT. The process of factoring-out or extracting parasitics is referred to as “de-embedding” and is well known in the prior art.
As is also well known in the prior art, one method for de-embedding parasitics involves analyzing four special DUTs that are fabricated with the same process and in accordance with the same design specifications as the DUT of interest.
FIGS. 1
a-
1
d
depict representations of the four special DUTs, which are widely-known to those skilled in the art as “short,” “load,” “open,” and “thru.” For pedagogical reasons, the special DUTs in
FIGS. 1
a-
1
d
are depicted so as to accentuate their similarities and differences. In particular, each of the special DUTs are similar in that each comprises a first lead, lead
103
, that is electrically connected to a first contact pad (not shown) and second lead, lead
104
, that is electrically connected to a second contact pad (not shown). It is through these contact pads that the physical characteristics of the special DUTs are measured using external measuring equipment.
FIG. 1
a
depicts the “short” DUT, in which each of lead
103
and lead
104
are electrically shorted to ground.
FIG. 1
b
depicts the “load” DUT, in which lead
103
and lead
104
are each electrically connected to ground via a 50 ohm impedance.
FIG. 1
c
depicts the “open” DUT, in which lead
103
and lead
104
are not connected at all (i.e., there is a gap between leads
103
and
104
). Lastly,
FIG. 1
d
depicts the “thru” DUT, in which lead
103
and lead
104
are electrically shorted to each other, but are not shorted to ground. It should be noted that the distinction between the short DUT in
FIG. 1
a
and the thru DUT in FlG.
1
d
, is that the leads; of the thru DUT are not shorted to ground.
As is well-known in the prior art, test signals are applied to each of the four special DUTs and the responses are measured. From these measurements, the parasitics of the leads can be determined and applied in well-known fashion to de-embed the parasitics and reveal the “true” parameters of the nominal DUT.
Although this technique for de-embedding parasitics is well known and widely used, its use is problematic in some applications. In particular, integrated circuits with conductive substrates (e.g., silicon substrates, etc.) that operate at high frequencies generate particularly strong parasitics that hinder the de-embedding process. Therefore, the need exists for a means to de-embed parasitics associated with devices formed on conductive substrates and that operate at high frequencies.
SUMMARY OF THE INVENTION
Some embodiments of the present invention are capable of de-embedding parasitics without some of the costs and restrictions associated with means for doing so in the prior art. In particular, some embodiments of the present invention provide structures on the integrated circuits that mitigate the severity of parasitics. Furthermore, some embodiments of the present invention are particularly well-suited for use with integrated circuits that have conductive substrates and that operate at high frequency.
And still furthermore, some integrated circuits formed in accordance with the present invention are well-suited as calibration standards for test equipment. In other words, some integrated circuits formed in accordance with the present invention are well-suited for distribution to a plurality of locations so that the integrated circuit test equipment at those locations can be calibrated to a common benchmark.
In the illustrative embodiments described below, conductive elements are used to construct structures near and/or around the leads to and from the DUT. When the structures are grounded, they function to (at least) partially shield the leads to and from the DUT in a manner that is analogous to stripline, microstrip and coaxial cable. Because the electric fields emanating from the leads terminate in the grounded structures and not in the conductive substrate of the integrated circuit, the severity of the parasitics in those leads can be substantially mitigated. This facilitates their measurement and subsequent de-embedding.
The first illustrative embodiment of the present invention is an integrated circuit comprising: a first pad, a first lead, a second pad, and a second lead made from a first conductive layer; a substrate; a first plate made from a second conductive layer that is between and electrically insulated from the first lead and the substrate; and a second plate made from the second conductive layer that is between and electrically insulated from the second lead and the substrate.


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C. Wan et al., “A New Technique for In-Fixture Calibration Using Standards of Constant Length,” IEEE Transactions on Microwave Theory, vol. 46, No. 9, Sep. 1998, pp. 1318-1320.

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