Article comprising a lattice-mismatched semiconductor heterostru

Details Article comprising a lattice-mismatched semiconductor heterostru Article comprising a lattice-mismatched semiconductor heterostru

1991-03-18

1992-02-25

Epps, Georgia

357 16, 357 30, H01L 2904

Patent

active

050917676

ABSTRACT:
Disclosed are strained layer heteroepitaxial structures (e.g., GeSi/Si) that can have low threading dislocation density as well as a substantially planar surface. Furthermore, a large fraction (e.g., >90%) of the total surface are of the structure can be available for device processing. These advantageous features are achieved through utilization of novel "dislocation sinks" on or in the substrate whose height parameter h is less than or about equal to the thickness of the strained heteroepitaxial layer on the substrate. Exemplarily, h.gtoreq.h.sub.c, where h.sub.c is the critical thickness associated with misfit dislocation generation in the substrate/overlayer combination.

REFERENCES:
patent: 4632712 (1986-12-01), Fan et al.
patent: 4872046 (1989-10-01), Morkoc et al.
patent: 5032893 (1991-07-01), Fitzgerald, Jr. et al.

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