Arrays of nonvolatile memory cells wherein each cell has two...

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays

Reexamination Certificate

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C257S204000, C257S206000, C257S207000, C257S208000, C257S209000, C257S210000, C257S211000, C257S314000, C257S316000, C257S390000, C257S391000, C257S905000, C257S909000, C257S920000, C438S128000, C438S129000, C438S587000, C438S588000, C438S598000, C438S599000

Reexamination Certificate

active

06885044

ABSTRACT:
In a nonvolatile memory array in which each cell (110) has two floating gates (160), for any two consecutive memory cells, one source/drain region (174) of one of the cells and one source/drain region of the other one of the cells are provided by a contiguous region of the appropriate conductivity type (e.g. N type) formed in a semiconductor substrate (120). Each such contiguous region provides source/drain regions to only two of the memory cells in that column. The bitlines (180) overlie the semiconductor substrate in which the source/drain regions are formed. The bitlines are connected to the source/drain regions.

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