Array-word-organized display memory and address generator with t

Details Array-word-organized display memory and address generator with t Array-word-organized display memory and address generator with t

1986-11-21

1988-09-20

Harkcom, Gary V.

Boots, shoes, and leggings

365238, 364518, G06F 1200, G06F 1300

Patent

active

047730447

ABSTRACT:
An array-word-organized memory system comprising a plurality of columns and rows of memory chips, an address bus routed through all of the memory chips, a plurality of selectable CAS lines wherein one of the CAS lines is routed through each one of said plurality of columns of memory chips and a plurality of selectable RAS lines wherein one of the RAS lines is routed through each one of said plurality of rows of memory chips. In operation, selected X and Y addresses are applied to the memory chips together with the strobing of selected ones of the CAS and RAS lines during four sequential time periods for addressing arbitrary arrays of pixels stored in the memory chips.

REFERENCES:
patent: 4183058 (1980-01-01), Taylor
patent: 4395700 (1983-07-01), McCubbrey et al.
patent: 4497024 (1985-01-01), Roth
patent: 4593642 (1985-09-01), Hansen
patent: 4608678 (1986-08-01), Threewitt
patent: 4683555 (1987-07-01), Pinkham
patent: 4691295 (1987-09-01), Erwin et al.
patent: 4725987 (1988-02-01), Cates

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