Array with amorphous silicon TFTs in which channel leads overlap

Details Array with amorphous silicon TFTs in which channel leads overlap Array with amorphous silicon TFTs in which channel leads overlap

1995-12-22

1998-02-10

Tran, Minh-Loan

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

257 59, 257 72, 359 59, H01L 2904

Patent

active

057172234

ABSTRACT:
An array includes cells, each with a bottom gate amorphous silicon thin film transistor (a-Si TFT). Each a-Si TFT has an undoped amorphous silicon layer over its gate region and extending beyond its edges. Each a-Si TFT also has an insulating region with edges approximately aligned with the edges of its gate region. Two channel leads of doped semiconductor material such as microcrystalline silicon or polycrystalline silicon are on the undoped amorphous silicon layer, each overlapping an edge of the insulating region by a distance that is no more than a maximum overlap distance, which in turn is no more than 1.0 .mu.m.

REFERENCES:
patent: 5274250 (1993-12-01), Miyake et al.
patent: 5324674 (1994-06-01), Possin et al.
patent: 5391507 (1995-02-01), Kwasnick et al.
patent: 5396072 (1995-03-01), Schiebel et al.
patent: 5462885 (1995-10-01), Nasu et al.
patent: 5466620 (1995-11-01), Bang
patent: 5471330 (1995-11-01), Sarma
patent: 5473168 (1995-12-01), Kawai et al.
patent: 5486939 (1996-01-01), Fulks
patent: 5491347 (1996-02-01), Allen et al.
Kanichi, J., Hasan, E., Griffith, J., Takamori, T., and Tsang, J.C., "Properties of High Conductivity Phosphorous Doped Hydrogenated Microcrystalline Silicon and Application in Thin Film Transistor Technology," Mat. Res. Soc. Symp. Proc., vol. 149, 1989, pp. 239-246.
Lustig, N., and Kanicki, J., "Gate dielectic and contact effects in hydrogenated amorphous silicon-silicon nitride thin film transistors," J. Appl. Phys., vol. 65, May 1989, pp. 3951-3957.
Wu, I-W., Lewis, A.G., Huang, T.-Y., and Chiang, A., "Performance of Polysilicon TFT Digital Circuits Fabricated with Various Processing Techniques and Device Architectures," SID 90 Digest, 1990, pp. 307-310.
Miura, Y., Jinnai, T., Kakkad, R., and Ibaraki, N., "A Five-Mask a-Si TFT-Array Process with ITO-Metal Double-Layer Data-Lines and Poly-Si Source-Drains," AM-LCD 95 Digest of Technical Papers, Aug. 1995, pp. 75-78.
Tanaka, Y., Shibusawa, M., Dohjo, M., Tomita, O., Uchikoga, S., and Yamanaka, H., "A 13.8-in.-Diagonal High-Resolution Multicolor TFT-LCD for Workstations," SID 92 Digest, May 1992, pp. 43-46.

Affiliated with

Also associated with

Rating

Array with amorphous silicon TFTs in which channel leads overlap does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Array with amorphous silicon TFTs in which channel leads overlap, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Array with amorphous silicon TFTs in which channel leads overlap will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2079165