Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2001-02-23
2004-05-18
Kim, Kenneth S. (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S010000, C712S011000, C712S015000, C712S017000
Reexamination Certificate
active
06738891
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a processor to execute processing a desired operation according to a program prepared therefor, and in particular, to an array-type processor including a plurality of processor elements arranged in a two-dimensional array shape.
DESCRIPTION OF THE PRIOR ART
The known programmable devices include various types of microprocessors in which instructions or commands stored in a memory are read in an order therefrom and are sequentially executed.
That is, in such a microprocessor, instructions each of which executes quite simple processing are ordered in a combination and are executed in an order to execute a target sequence of processing.
However, only several instructions can be simultaneously executed by one microprocessor. This limits improvement of processing performance or capacity.
Specifically, when the same processing is to be executed for a large amount of data, it is necessary to repeatedly execute sequential processing. Therefore, processing performance cannot be improved.
To surmount the limitation, a technique to concurrently (simultaneously) execute instructions by a plurality of processor elements is already known. Concretely, there exist various techniques depending on electric connections between the processor elements.
In the “Introduction To The Configurable, Highly Parallel Computer” (IEEE Computer, January 1982), Lawrence Snyder proposed one of the techniques. According to the proposal, a plurality of processor elements are disposed in an array shape and are electrically connected to each other using programmable switches (to be referred to as a first prior art technique hereinbelow).
The microprocessor of the first prior art technique executes concurrent processing by a plurality of processors to improve processing performance when compared with processing executed by one processor. Since processor elements are electrically connected by programmable switches, the electric connections between the elements can be established according to a purpose. Particularly, efficient processing can be executed in applications of data processing fields.
In the microprocessor, different kinds of processing, that is, processing based on an operating unit such as a data path and processing of a random logic circuit such as a control circuit are executed only by an array section of each processor element. It is therefore necessary to add general processing capacity to each processor element.
To meet requirements for miniaturization and high performance of microprocessors, a technique to customize the function of each processor element for it processing purpose is to be developed. However, the technique is quite difficult and hence there arises a problem that the requirements for miniaturization and high performance of microprocessors cannot be satisfied.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an array-type processor, devised to remove the problem of the prior art, including processor elements arranged in an array shape and electrically connected by programmable switches. The array-type processor includes a data path section to primarily conduct processing of operation and a state transition control section configured for easy implementation of a state transition function or unit to control state transition. Each section is customized for each processing purpose to thereby miniaturize its size and to improve processing performance.
To achieve the object above in accordance with the present invention, there is provided an array-type processor comprising a state transition control section including a state transition table memory for storing a state transition table in which transition rules between a plurality of operation states are written, and a sequencer section for controlling, using the state transition table memory, transitions between the operation states and for determining the operation states at a particular point of time; and a data path section independent of said state transition control section, including a plurality of processor elements for executing processing of operations according to the operation states determined by said state transition control section and a plurality of programmable switch elements for connecting the processor elements to each other according to the operation states determined by said state transition control section. The processor elements and said programmable switch elements are electrically connected in a two-dimensional array shape. Each said processor element includes an instruction code memory for storing a plurality of instruction codes, an instruction decoder for decoding an instruction code read from said instruction code memory, and an operating section for executing processing of operation according to the instruction code decoded by said instruction decoder. Each said programmable switch element includes a connection layout information memory for storing a plurality of sets of connection layout information, the information indicating a connection layout between said processor elements and said programmable switch elements and/or between said programmable switch elements.
As above, the data path section to primarily conduct operation and the state transition control section are separated from each other and each there of is configured in a customized manner according to its processing purpose. Therefore, the operation and the control operation can be efficiently implemented and the processing can be effectively executed. This minimizes the array-type processor in size, and processing performance is improved.
Additionally, in accordance with the present invention, in the array-type processor, the state transition control section conducts a control operation according to a transition of the operation state by said state transition control section itself and/or a transition of the operation state by inputting an event from said data path section and/or a transition of the operation state by inputting an event from an external device.
The configuration allows the array-type processor to carry out a flexible control operation for detailed items and hence processing performance is improved.
Moreover, in accordance with the present invention, the array-type processor further comprises an operation control bus for electrically connecting said state transition control section to said data path section. The state transition control section outputs an address of said instruction code memory and/or an address of said connection layout information memory via said operation control bus according to the operation states at a particular point of time.
Thanks to the structure, the array-type processor can efficiently delivers control signals from the state transition control unit to the processor elements and the programmable switch elements.
Furthermore, in accordance with the present invention, the array-type processor further comprises one or more said operation control buses. The state transition control section outputs the address to said operation control buses. Each of the processor elements and/or each of the programmable switch elements select/selects one of said operation control buses to input the address.
In consequence, the array-type processor can effectively operate the processor elements and hence processing performance is increased.
In addition, in accordance with the present invention, in the array-type processor, the state transition control section concurrently supplies independent said addresses respectively to said processor elements and respectively to said programmable switch elements.
In this constitution, the array-type processor can effectively operate the processor elements in the data path section, which improves processing performance.
Furthermore, in accordance with the present invention, in the array-type processor, the processor elements and/or the programmable switch elements are classified into groups. The address is supplied to one of the groups.
Consequently, the array-type processor can effectively
Fujii Taro
Furuta Koichiro
Motomura Masato
Dickstein Shapiro Morin & Oshinsky LLP.
Kim Kenneth S.
NEC Corporation
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