Array testing system on array substrate having multiple cells

Details Array testing system on array substrate having multiple cells Array testing system on array substrate having multiple cells

2003-04-25

2004-11-30

Parker, Kenneth (Department: 2871)

Liquid crystal cells, elements and systems

Nominal manufacturing methods or post manufacturing...

Defect correction or compensation

C324S701000

Reexamination Certificate

active

06825911

ABSTRACT:

The present application claims the benefit of Korean Patent Application No. 2002-0088488 filed in Korea on Dec. 31, 2002, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an array substrate for use in liquid crystal display devices, and more particularly, to an array substrate having multiple cells and an array testing system implanted thereon.
2. Discussion of the Related Art
A liquid crystal display device uses the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. Liquid crystal molecules have a definite alignment orientation due to their long, thin shapes. The alignment orientation can be controlled by application of an electric field. Accordingly, the alignment of the liquid crystal molecules can be altered by changing the applied electric field. Due to the optical anisotropy of the liquid crystal molecules, refraction of incident light is dependent upon the orientation of the aligned liquid crystal molecules. Therefore, by controlling the electric field applied to the liquid crystal molecules, an image can be produced by the liquid crystal display device.
Liquid crystal display (LCD) devices have wide application in office automation (OA) and video equipment because of their light weight, thin design, and low power consumption characteristics. Among the different types of LCD devices, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, offer high resolution and superiority in displaying moving images. A typical LCD panel has an upper substrate, a lower substrate and a liquid crystal material layer interposed therebetween. The upper substrate, commonly referred to as a color filter substrate, includes a common electrode and color filters. The lower substrate, commonly referred to as an array substrate, includes switching elements, such as thin film transistors (TFTs), and pixel electrodes, for example.
As previously described, operation of an LCD device is based on the principle that the alignment direction of the liquid crystal molecules is dependent upon an applied electric field between the common electrode and the pixel electrode. Accordingly, the liquid crystal molecules function as an optical modulation element having variable optical characteristics that depend upon polarity of the applied voltage.
When fabricating the liquid crystal panel, a first substrate (i.e., lower substrate or array substrate) and a second substrate (i.e., upper substrate or color filter substrate) are previously fabricated and then bonded and aligned to each other. Thereafter, liquid crystal material is interposed between the first and second substrates. Then, the attached substrates are divided into individual liquid crystal cells.
The fabrication process for the first substrate includes many thin film deposition processes to form insulating layers, semiconductor layers and conductive layers, as well as many etching and/or patterning processes to form desired layer patterns, thereby forming a plurality of thin film transistors, pixels and other layer elements. At this time of manufacturing the first substrate, a plurality of array cells each including the plurality of thin film transistors and array elements are formed on a large substrate to decrease fabrication process steps. In such a manner, a plurality of color filter cells each corresponding to each array cell are formed on a large substrate that is for the second substrates of the liquid crystal display panel. Those two large substrates respectively having the plurality of array cells and color filter cells are attached to each other with the liquid crystal layer interposed therebetween, thereby forming the liquid crystal display panel. Thereafter, the attached liquid crystal panel is cut and divided into the liquid crystal cells.
Before attaching the two large substrates, the large first substrate (array substrate) is tested by an array testing system to analyze whether the large array substrate has any defects. The large first substrate is often called as an array testing substrate because this substrate has many array cells for the array test with a plurality of test pads and test lines.
FIG. 1
is a plan view illustrating an array testing substrate having a plurality of array cells according to the related art.
FIG. 2
is an enlarged plan view of an array cell of FIG.
1
and array cells adjacent thereto.
As mentioned before, the array substrate for the array test includes a plurality of array cells
10
. Each array cell
10
has divided regions of a display area
20
, a non-display area
30
and a pad area
40
. The display area
20
includes a plurality of pixels P each having a thin film transistor T to show images. The non-display area
30
is disposed surrounding the display area
20
. The pad area
40
is disposed just adjacent to bottom and left sides of the non-display area
30
.
In the display area
20
, as shown in
FIG. 2
, a plurality of gate lines
22
and a plurality of data lines
26
are disposed on the substrate, respectively, in columns and rows. The gate lines
22
perpendicularly cross the data lines
26
, thereby defining the pixels P in a matrix type. A pixel electrode
59
is disposed corresponding to each pixel P, and the thin film transistor T is disposed at a corner of the pixel P near the crossing of the gate and data lines
22
and
26
. Each thin film transistor T includes a gate electrode (not shown) that extends from the gate line
22
, a source electrode (not shown) that extends from the data line
26
, and a drain electrode (not shown) that is connected with the pixel electrode
59
.
The non-display area
30
is a region where a seal pattern is placed to attach the color filter substrate to the array substrate. Since the non-display area
30
does not include any pixels P, the non-display area
30
would be unable to show images when the array cell
10
is adopted in the liquid crystal display panel.
A plurality of gate pads
24
and a plurality of data pads
28
are disposed in the pad area
40
. The plurality of gate pads
24
are connected with the plurality of gate lines
22
, respectively, and disposed at the bottom portion of the pad area
40
. In this same manner, the plurality of data pads
28
are connected with the plurality of data lines
22
, respectively, and are disposed at the left portion of the pad area
40
. Thus, the pad area
40
is divided into a gate pad area
42
where the gate pads
24
are placed, and a data pad area
44
where the data pads
28
are placed. The gate pads
24
and the data pads
28
act as connection terminals that electrically connect the gate and data lines
22
and
26
to the external driving circuits.
Still referring to
FIGS. 1 and 2
, the array substrate includes the plurality of array cells
10
and a plurality of test pads
50
each corresponding to each array cell
10
. The array substrate also includes test lines
60
each connecting the test pad
50
to the corresponding array cell
10
. The test pad
50
acts as an input terminal by way of receiving signals from the array testing apparatus during the array test.
In
FIG. 1
, the test pads
50
are generally disposed at top and bottom peripheries of the large array substrate. The test line
60
connects the test pad
50
to the gate and data pads
24
and
28
of the corresponding array cell
10
such that the test line
60
has a one-to-one connection between the test pad
50
and the array cell
10
. Each test pad
50
includes at least one gate test pad
52
that is connected with the gate pads
24
of the array cell
10
, and at least one data test pad
54
that is connected with the data pads
28
. In this manner, the test line
60
is divided into a gate test line
62
that connects the plurality of gate pads
24
to the gate test pad
52
and a data test line
64
that connects the plurality of data pads
28
to the data test pad
54
. These test pads
50
and test lines
60
can be formed together with

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