Array substrate with bus lines takeout/terminal sections having

Details Array substrate with bus lines takeout/terminal sections having Array substrate with bus lines takeout/terminal sections having

1996-10-04

1998-11-10

Sikes, William L.

Liquid crystal cells, elements and systems

Particular structure

Having significant detail of cell structure only

349152, 349139, 257 59, G06F 11343, G06F 11345, H01L 2904

Patent

active

058351779

ABSTRACT:
An array substrate includes plural scanning lines (111); a thin film transistor (112) having a first dielectric film (115), (117), a semiconductor film (120) thereon, and a source electrode (126b) electrically coupled to the semiconductor film (120) and a drain electrode (126a); a signal line (110) as taken out of the drain electrode (126a) to extend at substantially right angles to the scanning lines (111); and a pixel electrode (131) electrically connected to the source electrode (126b), wherein the pixel electrode (131) is electrically connected to the source electrode (126b) through a second dielectric film (127) as disposed on at least the signal line (110) while the pixel electrode (131) overlaps an elongate region (113) from its neighboring scanning line (111) through the first and second dielectric films (115), (117), (127). With such an arrangement, an appropriate storage capacitor can be formed by causing the scanning lines and pixel electrode to overlap each other without having to decrease the manufacturing yield while enabling achievement of high aperture ratio.

REFERENCES:
patent: 4621260 (1986-11-01), Suzuki et al.
patent: 5187604 (1993-02-01), Taniguchi et al.
patent: 5264728 (1993-11-01), Ikeda et al.
patent: 5428250 (1995-06-01), Ikeda et al.
patent: 5483082 (1996-01-01), Takizawa et al.
patent: 5488498 (1996-01-01), Fujii et al.
patent: 5499131 (1996-03-01), Kim
patent: 5748179 (1998-05-01), Ito et al.

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