Array substrate of a liquid crystal display and method of...

Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal

Reexamination Certificate

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Details

C349S039000, C349S143000, C349S147000

Reexamination Certificate

active

06819368

ABSTRACT:

This application claims the benefit of Korean Patent Application No. 2001-36211, filed on Jun. 25, 2001, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to an array substrate of a liquid crystal display that is adaptive for improving an aperture ratio of a high-definition liquid crystal display. The present invention also is directed to a method of fabricating the array substrate of the liquid crystal display.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) of an active matrix driving system uses thin film transistors (TFTs) as switching devices to display a natural moving picture. Since such an LCD can be made into a smaller device in size than the existing Brown tube, LCDs have been widely used in monitors for personal computers or notebook computers as well as office automation equipment such as copy machines, etc. and portable equipment such as a cellular phones and a pagers, etc.
Such a liquid crystal display includes liquid crystal injected between a lower substrate provided with switching devices each consisting of a gate electrode, a gate insulating film, an active layer, an ohmic contact layer, source and drain electrodes, pixel electrodes, and an upper substrate provided with color filters.
Referring to
FIG. 1
, an array substrate of the conventional liquid crystal display is divided into a transistor area T
1
and a storage capacitor area C
1
.
The transistor area T
1
is provided with a TFT consisting of a gate electrode
13
, a gate insulating film
17
(shown in FIG.
2
), an active layer
19
(shown in FIG.
2
), an ohmic contact layer
21
(shown in
FIG. 2
) and source and drain electrodes
23
and
25
. The drain electrode
25
of the TFT electrically contacts a pixel electrode
35
via a first contact hole
31
.
The storage capacitor area C
1
is positioned at the center of the pixel, and is provided with a common wire
15
formed at the lower portion thereof having the gate insulating film
17
(shown in
FIG. 2
) therebetween and a storage electrode
27
formed at the upper portion thereof. In this case, the storage electrode
27
is connected to the pixel electrode
35
via a second contact hole
33
in a passivation layer
29
(shown in
FIG. 2
) formed thereon. A storage capacitor Cst (shown in
FIG. 2
) is provided between the common wire
15
, which is a lower electrode, and the storage capacitor
27
, which is an upper electrode, with the gate insulating film
17
therebetween. This storage capacitor Cst plays a role to improve a sustaining characteristic of a liquid crystal application voltage in a non-selection interval and stabilizes gray scale display.
A method of fabricating such a liquid crystal display will be described with reference to FIG.
2
.
First, a gate electrode
13
is formed at the transistor area T
1
of the substrate
40
, and a common wire
15
is formed at the capacitor area C
1
arranged at the middle portion of the pixel. Subsequently, a gate insulating film
17
made from an insulating material such as silicon nitride or silicon oxide is provided to cover the entire surfaces of the gate electrode
13
, the common wire
15
and the substrate
40
.
Next, an active layer
19
is formed at a portion corresponding to the gate electrode
13
on the gate insulating film
17
. An ohmic contact layer
21
is formed at a portion excluding a portion corresponding to the gate electrode
13
at each side of the active layer
19
. The active layer
19
is made from amorphous silicon or polycrystalline silicon, which is not doped with an impurity, while the ohmic contact layer
21
is made from amorphous silicon or polycrystalline silicon, which is doped with a n-type or p-type impurity at a high concentration.
Then, source and drain electrodes
23
and
25
are formed at the transistor area T
1
on the gate insulating film
17
in such a manner to cover the ohmic contact layer
21
. At the same time, a storage electrode
27
is formed at a portion corresponding to the common wire
15
having the gate insulating film
17
therebetween. The source and drain electrodes
23
and
25
and the storage electrode
27
are made from a metal such as molybdenum (Mo), chromium (Cr), or a molybdenum alloy such as MoW, MoTa or MoNb, etc.
Thereafter, a passivation layer
29
is formed on the gate insulating film
17
in such a manner to cover the above-mentioned structure. The passivation layer
29
is made from an inorganic insulating material such as silicon nitride or silicon oxide, etc. and an organic material having a small dielectric constant such as an acrylic organic compound, benzocyclobutene (BCB) or perfluorocyclobutane (PFBC), etc.
A first contact hole
31
for exposing the drain electrode
25
and a second contact hole
33
for exposing the storage electrode
17
are provided in the passivation layer
29
. A pixel electrode
35
contacting the drain electrode
25
and the storage electrode
27
via the first and second contact holes
31
and
33
is formed on the passivation layer
29
. The pixel electrode
35
is made from a transparent conductive material such as indium-tin-oxide (ITO), tin-oxide (TO) or indium-zinc-oxide (IZO), etc.
An array substrate
40
provided with the transistor area T
1
and the storage capacitor area C
1
is opposed and joined to an upper substrate provided with black matrices and color filters (not shown) having a liquid crystal therebetween. At this time, since the black matrices cannot control an arrangement of liquid crystal molecules at an area generating a disinclination line in which a liquid crystal alignment is changed discontinuously, the black matrices hide the transistor area T
1
and the storage capacitor area C
1
including the common wire
15
positioned at the center of the pixel electrode
35
. To this end, the black matrices are formed divided into two parts on the transistor area T
1
and the storage capacitor area C
1
within one pixel in consideration of a joint margin (about 5 &mgr;m) of the upper substrate to the array substrate
40
.
Therefore, apertures X and Y (shown in
FIG. 1
) are largely reduced by the black matrices. As a result, a reduction of the apertures X and Y raises a problem in that it is impossible to cope with a high-definition liquid crystal display having a decreased pixel size.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an array substrate of a liquid crystal display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An advantage of the present invention is to provide an array substrate of a liquid crystal display and a fabricating method thereof that is adaptive for improving an aperture ratio of a high-definition liquid crystal display.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, an array substrate of a liquid crystal display according to one aspect of the present invention includes a substrate; a gate wire and a common wire provided on the substrate; a gate electrode protruded from the gate wire; a gate insulating film formed to cover the gate wire and the gate electrode; a semiconductor layer formed on the gate insulating film in correspondence with the gate electrode; a source electrode provided on the semiconductor layer and the gate insulating film and connected to the data wire; a drain electrode provided on the semiconductor layer and the gate insulating film and opposed to the sour

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