Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2006-01-31
2006-01-31
Coleman, W. David (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C438S411000, C438S421000
Reexamination Certificate
active
06992364
ABSTRACT:
A TFT array substrate has a PAI pattern, and the PAI pattern has an over-etched portion of the pure amorphous silicon layer. This over-etched portion prevents a short between the pixel electrode and the pure amorphous silicon layer (i.e., the active layer). The over-etched portion also enables the aperture ratio to increase a gate line over a said substrate; a data line over the said substrate being perpendicular to the gate line; a passivation layer covering the data line, the passivation layer divided into a residual passivation layer and a etched passivation layer; a doped amorphous silicon layer formed under the data line and corresponding in size to the data line; a pure amorphous silicon layer formed under the doped amorphous silicon layer and having a over-etched portion in the peripheral portions, wherein the over-etched portion is over-etched from the edges of the residual passivation layer toward the inner side; an insulator layer under the pure amorphous silicon layer; a TFT formed near the crossing of the gate line and the data line; and a pixel electrode overlapping the data line and contacting the TFT.
REFERENCES:
patent: 5355011 (1994-10-01), Takata
patent: 5552909 (1996-09-01), Onisawa et al.
patent: 5602047 (1997-02-01), Tsai et al.
patent: 5605847 (1997-02-01), Zhang
patent: 5610082 (1997-03-01), Oh
patent: 5672523 (1997-09-01), Yamamoto et al.
patent: 5811328 (1998-09-01), Zhang et al.
patent: 5814836 (1998-09-01), Hyun
patent: 5844647 (1998-12-01), Maruno et al.
patent: 5886761 (1999-03-01), Sasaki et al.
patent: 5917563 (1999-06-01), Matsushima
patent: 5920082 (1999-07-01), Kitazawa et al.
patent: 5963797 (1999-10-01), Hyun
patent: 5969702 (1999-10-01), Bae
patent: 5982460 (1999-11-01), Zhang et al.
patent: 6067132 (2000-05-01), Kim
patent: 6078365 (2000-06-01), Ueda et al.
patent: 6097453 (2000-08-01), Okita
patent: 6195140 (2001-02-01), Kubo et al.
patent: 6207480 (2001-03-01), Cha et al.
patent: 6274400 (2001-08-01), Jen
patent: 6562671 (2003-05-01), Ohnuma
patent: 6624013 (2003-09-01), Kawasaki et al.
patent: 6875645 (2005-04-01), Lai
Jung Yu-Ho
Kim Hu-Sung
Kim Yong-Wan
Kwak Dong-Yeung
Lee Woo-Chae
Coleman W. David
LG.Philips LCD Co. , Ltd.
Morgan & Lewis & Bockius, LLP
Nguyen Khiem
LandOfFree
Array substrate for use in LCD device and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Array substrate for use in LCD device and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Array substrate for use in LCD device and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3567719