Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
2000-10-25
2003-11-25
Ton, Toan (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S054000, C438S144000
Reexamination Certificate
active
06654074
ABSTRACT:
CROSS REFERENCE
This application claims the benefit of Korean Patent Application No. 1999-46344, filed on Oct. 25, 1999, under 35 U.S.C. §119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for use in a liquid crystal display (LCD) device and a method of manufacturing the same.
2. Description of Related Art
A typical LCD device includes upper and lower substrates with a liquid crystal layer interposed therebetween. The upper substrate includes a color filter and a common electrode. The lower substrate includes a switching element and a pixel electrode and is called an array substrate.
FIG. 1
is a plan view illustrating an array substrate for use in a conventional LCD device. As shown in
FIG. 1
, the LCD device includes gate lines
13
arranged in a transverse direction and data lines
19
arranged in a longitudinal direction perpendicular to the gate lines
13
. Gate pads
11
are formed at one terminal portion of the gate lines
13
, and odd and even data pads
15
a
and
15
b
are formed at one terminal portion of the odd and even data lines
19
a
and
19
b
, respectively. Gate shorting bars
23
electrically connects the gate lines
13
with each other. Data shorting bars
29
electrically connect the data lines
19
with each other. Thin film transistors (TFTs) are arranged a crossing point of the gate and data lines
13
and
19
. Pixel electrodes “P” are arranged on a region defined by the gate and data lines
13
and
19
.
The gate line
13
includes odd and even gate lines, but one of the odd and even gate lines is not shown. The data lines
19
also include odd and even data lines
19
a
and
19
b
. The gate shorting bars includes odd and even gate shorting bars. The odd gate shorting bars connect the odd gate lines with each other, and the even gate shorting bars connect the even gate lines with each other, respectively, through the gate pads
11
. The odd and even gate shorting bars are opposite to each other. The data shorting bars
29
also includes odd and even data shorting bars
29
a
and
29
b
. The odd data shorting bars
29
a
connect the odd data lines
19
a
with each other, and the even data shorting bars
29
b
connect the even data lines
19
b
with each other.
In
FIG. 2
(which shows portion A of
FIG. 1
in more detail), each of the TFTs includes a gate electrode
10
, a source electrode
17
, a drain electrode
18
, and an active layer
16
. The gate electrode
10
extends from the gate line
13
, and the source electrode
17
extends from the data line
19
. The source and drain electrodes
17
and
18
are spaced apart from each other and overlay opposite sides of the active layer
16
, respectively. The drain electrode
18
is electrically connected with the pixel electrode “P” through a contact hole
5
. The active layer
16
extends from an active line
28
under the data line
19
.
The shorting bars
23
and
29
are provided for a short-circuit test between the two adjacent gate lines or the two adjacent data lines. In other words, in case of the data lines
19
, as described above, since the odd shorting bars
29
a
connect the odd data lines
19
a
electrically and the even shorting bars
29
b
connect the even data lines
19
b
electrically, the odd and even shorting bars
19
a
and
19
b
are electrically separated from each other. Therefore, it can be tested whether the two adjacent data or gate lines are short or not.
In general, the even data shorting bar
29
b
is patterned along with the gate line
13
, and later the odd data shorting bar
29
a
is formed at the same time as the data lines
19
a
and
19
b
, and then the even data shorting bar
29
b
is electrically connected with the odd data lines
19
a
while the pixel electrode P is formed. Therefore, the even data shorting bar
29
b
is made of the same metal as the data line, and the odd data shorting bar
29
a
is made of the same metal as the gate line.
The gate and data lines
13
and
19
are made of a conductive metal such as Cr, W and Mo, which are flexible materials. An insulating layer (not shown) that insulates each of the elements of the LCD device is made of SiO
2
or SiNx. The active layer
16
and an active line
28
are made of semiconductor material such as amorphous silicon and polysilicon, which are very hard materials. Since the active line
28
that is relatively hard is formed under the data line
19
, the data line
19
is not bent, whereupon a break or open circuit condition of the data line
19
is prevented. For example, when the array substrate is bent during its conveyance, the data line
19
may be cracked, leading to the open circuit.
To complete the array substrate described above, a depositing technique, a photolithography technique, and an etching technique are repeated several times.
Of these, the etching technique includes a dry-etching and a wet-etching. The dry-etching includes a plasma dry-etching, an ion beam milling etching, and a reactive ion etching. In wet-etching, acids and other chemical solutions are used as an etching. In chemical dry-etching, for example, the plasma dry-etching, plasma is used to generate gas radicals such as fluorine radicals in order to etch any portions of a thin film that are not covered by photoresist. In physical dry-etching, for example, ion beam milling etching, an ion beam is used in order to etch any portions of a thin film that are not covered by a photoresist.
Such a dry-etching technique requires a high electric field, so that static electricity may occur and be locally accumulated on the gate and data lines formed previously during the dry-etching process that is performed several times. The accumulated charges may cause a short-circuit between the data line and the gate electrode, for example, a portion C of FIG.
2
.
In other words, note that the even data shorting bar
29
b
is formed together with the even data lines
19
b
. Since the gate shorting bars
23
also serve to discharge the static charges accumulated on the gate lines
13
, a short-circuit between the data line and the gate line due to the accumulated charges may not occur. In the same way, the odd data lines
19
a
are connected to the odd data shorting bar
29
a
and so the charges are discharged, a short-circuit an odd data line
19
a
and a gate line
13
due to the accumulated charges may not occur. However, the even data shorting bar
29
b
is electrically connected with the even data lines
19
b
at a later time, when the pixel electrode is formed. Thus charges on the even data lines
19
b
are not discharged during a process of manufacturing the TFT, and so a short circuit between the odd data line
19
b
and the gate electrode can occur due to the accumulated static charges, leading to low manufacturing yields.
For the foregoing reasons, there is a need for an array substrate having a structure that prevents the effect of the static electricity generated during a process of manufacturing a thin film transistor.
SUMMARY OF THE INVENTION
To overcome the problems described above, embodiments of the present invention provide array substrates (and methods of making the same) for use in a liquid crystal display device, which has a structure that prevents the effect of the static electricity generated during the manufacturing process.
The present invention, in part, provides an array substrate for use in a liquid crystal display device, the array substrate including: gate lines arranged in a transverse direction and organized as odd and even gate lines; data lines arranged in a longitudinal direction perpendicular to the gate lines, and organized as odd and even data lines; gate pads arranged at a terminal portion of the gate lines, and organized as odd and even gate pads; data pads arranged at a terminal portion of the data lines, and being organized as odd and even data pads; gate shorting bars and organized as odd and even gate shorting bars, the odd gat
Ha Young-Hun
Kim Hyeung-Soo
Lee Seong-Su
Akkapeddi P. R.
Birch & Stewart Kolasch & Birch, LLP
LG. Philips LCD Co. Ltd.
Ton Toan
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