Array substrate for LCD device and method of fabricating the...

Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal

Reexamination Certificate

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C349S041000

Reexamination Certificate

active

06671010

ABSTRACT:

This application claims the benefit of Korean patent application No. 2000-72245, filed on Dec. 1, 2000 in Korea, which is hereby incorporated by reference as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to an array substrate having thin film transistors (TFTs) each implanting a compact structure.
2. Discussion of the Related Art
In general, liquid crystal display (LCD) devices make use of optical anisotropy and polarization properties of liquid crystal molecules to control arrangement orientation. The arrangement direction of the liquid crystal molecules can be controlled by an applied electric field. Accordingly, when an electric field is applied to liquid crystal molecules, the arrangement of the liquid crystal molecules changes. Since refraction of incident light is determined by the arrangement of the liquid crystal molecules, display of image data can be controlled by changing the electric field applied to the liquid crystal molecules.
Of the different types of known LCDs, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, are the subject of significant research and development because of their high resolution and superiority in displaying moving images.
The typical liquid crystal display (LCD) panel has an upper substrate, a lower substrate and a liquid crystal layer interposed therebetween. The upper substrate, commonly referred to as a color filter substrate, usually includes a common electrode and color filters. The lower substrate, commonly referred to as an array substrate, includes switching elements, such as thin film transistors (TFTs), and pixel electrodes.
FIG. 1
is an exploded perspective view illustrating a typical LCD device. An LCD device
11
includes an upper substrate
5
and a lower substrate
22
that are opposed to each other, and a liquid crystal layer
14
interposed therebetween. The upper substrate
5
and the lower substrate
22
are called a color filter substrate and an array substrate, respectively. On the upper substrate
5
, a black matrix
6
and a color filter layer
7
including a plurality of red (R), green (G), and blue (B) color filters are formed. The black matrix
6
surrounds each color filter such that an array matrix feature is formed. Further on the upper substrate
5
, a common electrode
18
is formed to cover the color filter layer
7
and the black matrix
6
.
On the lower substrate
22
on a side opposing the upper substrate
5
, thin film transistors (TFTs) “T” are formed in shape of an array matrix corresponding to the color filter layer
7
. In addition, a plurality of crossing gate and data lines
13
and
15
are positioned such that each TFT “T” is located near each crossing portion of the gate and data lines
13
and
15
. The crossing gate and data lines define a pixel region “P”. A pixel electrode
17
is formed on the pixel region “P”. The pixel electrode
17
is made of transparent conductive material, such as ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide), which has excellent light transmissivity.
In the above-mentioned LCD panel, the liquid crystal molecules of the liquid crystal layer
14
are arranged in accordance with the signals applied to the pixel electrode
17
through the TFT “T”. The light passing through the liquid crystal layer
14
is controlled by the arrangement of the liquid crystal molecules.
FIG. 2
is a partial plan view of a conventional array substrate of active matrix liquid crystal display (AM-LCD). As shown in
FIG. 2
, the array substrate
22
of an AM-LCD includes a thin film transistor “T”, a pixel electrode
17
and a storage capacitor “C”. A gate line
13
is arranged in a transverse direction and a data line is arranged perpendicular to the gate line
13
in the array substrate
22
. A pair of gate line
13
and data line
15
define a pixel region “P”. The TFT “T” includes a gate electrode
26
, a source electrode
28
, a drain electrode
30
and an active layer
24
, and is arranged at one corner of the pixel region “P” where the data line
15
crosses the gate line
13
. The gate electrode
26
extends longitudinally from the gate line
13
into the pixel region “P” and the source electrode
28
extends transversely from the data line
15
into the pixel region “P”. The drain electrode
30
is spaced apart from the source electrode
28
to form a channel region on the active layer
24
. The storage capacitor “C” is a storage-on-gate type capacitor in which a portion of the pixel electrode
17
overlaps a portion of the gate line
13
. The portion of the gate line
13
serves as a first capacitor electrode and the portion of the pixel electrode
17
serves as a second capacitor electrode. Although not shown in
FIG. 2
, an insulator serving as a dielectric layer in the storage capacitor is interposed between the gate line
13
and the pixel electrode
17
, thereby forming an MIM (metal-insulator-metal) structure.
The operation of the TFT “T” and the capacitance of the storage capacitor “C” have an influence on the operating characteristics of the array substrate shown in FIG.
2
. Therefore, it is very important that the structure and configuration of the TFT and storage capacitor should be designed and fabricated properly.
The thin film transistor (TFT) “T” generally has the channel region on the active layer
24
between the source and drain electrodes
28
and
30
. Thus, the operating characteristics of the TFT are dependent on the channel region's configuration, such as a channel width “W” and a channel length “L”. Furthermore, a portion of the drain electrode
30
overlaps a portion of the gate electrode
28
, thereby forming an overlapped area “M”. Due to this overlapped area “M”, a gate-drain parasitic capacitance C
gd
occurs in the TFT “T”. Since this parasitic capacitance C
gd
has a bad influence on the operating characteristics of the TFT, decreasing the parasitic capacitance C
gd
is a significant issue when designing the thin film transistor. In the thin film transistor, the parasitic capacitance can be given by following equation (1),
C
gd
=
ϵ



A
gd
d
gd
(
1
)
where A
gd
denotes the overlapped area “M”, d
gd
denotes a distance between the gate electrode
26
and the drain electrode
30
, and epsilon ∈ is the permittivity of the dielectric layer. From the above equation, it is easily noticeable that the parasitic capacitance C
gd
decreases as the overlapped area “M” becomes smaller.
Furthermore, the parasitic capacitance C
gd
deteriorates the liquid crystal layer and is closely related to a direct current offset voltage &Dgr;V
p
. The relation between C
gd
and &Dgr;V
p
is expressed by the following equation (2),
Δ



V
P
=
V
SC
-
V
PC
=
V
g



C
gd
C
t
(
2
)
where voltage V
sc
denotes a center voltage of a signal voltage, voltage V
pc
denotes a center voltage of the pixel electrode, voltage V
g
denotes voltage of the gate electrode, and the total capacity C
t
=C
gs
+C
S
(storage capacitor)+C
Lc
(liquid crystal capacitor). If C
gd
is much smaller than C
S
or C
LC
in the equation (2), the denominator C
t
equals C
s
+C
LC
, and will thus be assumed a constant. Accordingly, the magnitude of &Dgr;V
p
is proportional to the size of C
gd
. As the C
gd
becomes smaller, the operation characteristics of the array substrate improve.
The direct current offset voltage &Dgr;V
p
contributes to inferior display images by causing afterimages, image inconsistency and poor reliability of the LCD. Thus, to obtain superior video quality, the size of &Dgr;V
p
should be reduced. According to the equation (2), to lower the &Dgr;V
p
value, the C
gd
must also be lowered, which can be accomplished by decreasing the overlapped area “M”. Further, if the C
gd
is fixed at a certain value, the &Dgr;V
p
value is compensated by the common voltage.
However, the size of the overlapped area “M” varies

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