Array substrate for IPS mode liquid crystal display device

Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal

Reexamination Certificate

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C349S046000, C349S041000, C349S141000

Reexamination Certificate

active

06738110

ABSTRACT:

This application claims the benefit of Korean Patent Application No. 2001-87522, filed on Dec. 28, 2001 in Korea, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly, to an array substrate for In-Plane Switching (IPS) mode liquid crystal display device which displays superior images by preventing light leakage in an area adjacent to a thin film transistor region.
2. Discussion of the Related Art
A typical liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite orientation order in alignment resulting from their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by supplying an electric field to the liquid crystal molecules. In other words, as the alignment direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Because incident light is refracted to the orientation of the liquid crystal molecules due to the optical anisotropy of the aligned liquid crystal molecules, image data is displayed.
Active matrix liquid crystal display (AMLCD) devices, in which the thin film transistors and the pixel electrodes are arranged in the form of a matrix, are widely used because of their high resolution and superiority in displaying moving images. An array substrate for the in-plane switching (IPS) mode liquid crystal display (LCD) device will be described hereinafter with reference to the following figures.
FIG. 1
is a plan view of a pixel of an array substrate for a related art in-plane switching (IPS) mode liquid crystal display (LCD) device. In
FIG. 1
, a plurality of gate lines
12
and common lines
16
are horizontally formed on an array substrate
10
and are spaced apart from each other. A plurality of data lines
24
is vertically formed on the array substrate
10
and cross the gate lines
12
and the common lines
16
. The data line
24
defines a pixel region “P” by crossing the gate line
12
. A thin film transistor “T” is formed at a crossing point of the gate line
12
and the data line
24
. The thin film transistor “T” includes a gate electrode
14
, an active layer
20
, a source electrode
26
and a drain electrode
28
. The gate electrode
14
communicates with the gate line
12
and the source electrode
26
communicates with the data line
24
. The source electrode
26
has a U-shape surrounding the drain electrode
28
and the drain electrode
28
has an I-shape. A pixel electrode
30
that communicates with the drain electrode
28
and a common electrode
17
parallel with the pixel electrode
30
are formed in the pixel region “P”. The common electrode
17
communicates with the common line
16
. The pixel electrode
30
comprises an extension portion
30
a
, a vertical portion
30
b
and a horizontal portion
30
c
. The extension portion
30
a
of the pixel electrode
30
is extended from the drain electrode
28
and the vertical portion
30
b
of the pixel electrode
30
is vertically extended from the extension portion
30
a
The horizontal portion
30
c
of the pixel electrode
30
is formed over the common line
16
and connects the vertical portions
30
b
into one portion. The common electrode
17
comprises a horizontal portion
17
a
and a plurality of vertical portions
17
b
. The plurality of the vertical portions
17
b
of the common electrode
17
is arranged in an alternating order with the vertical portions
30
b
of the pixel electrode
30
. The horizontal portion
17
a
of the common electrode
17
connects the plurality of the vertical portions
17
b
into one portion. The vertical portions
17
b
of the common electrode
17
are spaced apart from the data line
24
. A storage capacitor “C” is formed in the pixel region “P”. The storage capacitor “C” uses a portion of the common line
16
as a first storage electrode and the horizontal portion
30
c
of the pixel electrode
30
as a second storage electrode.
A typical driving method of a pixel will be described hereinafter with reference to
FIG. 2
which-is a signal graph illustrating voltage signals of a gate electrode and a common electrode during a frame. The graph shows applying states of a gate voltage (V
g
) and a common voltage (V
com
) during a frame period. In
FIG. 2
, V
gh
and V
gl
show a high and a low state of the gate voltage V
g
and [V
dh
]V
d
respectively, and V
dl
show a high and a low state of the data voltage V
d
. As shown in the figure, a voltage of about +18 volts is applied when the gate voltage (V
g
) is in the on state and a voltage of about 5 volts is applied when the gate voltage (V
g
) is in an off state. A high-level data voltage (V
d
) is input when the gate voltage (V
g
) is in the on state and maintained until a next gate voltage (V
g
) reaches the on state. This voltage applying process fulfills a drive of liquid crystal in the pixel region. If the liquid crystal display (LCD) device is normally black mode, a black color is displayed when the voltage is not applied. However, a light leakage phenomenon occurs in region “A” of
FIG. 1
when the gate voltage (V
g
) is in the off state.
FIG. 3
is a plan view illustrating an electric field direction between the gate electrode and the common electrode when the gate voltage (V
g
) is in the off state according to the related art.
FIG. 4
is a plan view illustrating an alignment direction of liquid crystal molecules between the gate electrode and the common electrode when the gate voltage (V
g
) is in the off state according to the related art.
In
FIG. 3
, region “B” shows an electric field distribution in a region “E” between the gate electrode
14
and the common electrode
17
. In
FIG. 4
, region “F” is a long axis direction of the liquid crystal
19
and region “D” is a rubbing direction of a substrate. As shown in
FIG. 4
, the liquid crystal
19
is aligned parallel with the rubbing direction when the voltage is not applied. However, an electric potential difference actually exists in the region “A” between the gate electrode
14
and the common electrode
17
. Subsequently, the electric field distribution occurs, which has a certain direction, between the gate electrode
14
and the common electrode
17
. As shown in FIG.
3
and
FIG. 4
, the electric field direction is perpendicular to the long axes “F” of the liquid crystal
19
in the region between the gate electrode
14
and the common electrode
17
. The liquid crystal
19
will subsequently align according to the electric field direction when the gate voltage (V
g
) is in the off state. Accordingly, light irradiated from a backlight passes through the “A” region and thus the light leakage phenomenon occurs when the gate voltage (V
g
) is not applied at the normally black mode. Though a black matrix is generally formed on an upper substrate (not shown) in order to intercept the light leakage in the region “A”, it still may be difficult to display a high quality image if an aligning error of the upper and lower substrate occurs.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an array substrate for in-plane switching (IPS) mode liquid crystal display (LCD) device that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An advantage of the present invention is to provide the array substrate for in-plane switching (IPS) mode liquid crystal display (LCD) device in order to display a high quality image by preventing light leakage in a region between a gate electrode and a common electrode.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structur

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